From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Igor Mitsyanko" <i.mitsyanko@samsung.com>,
"Evgeny Voevodin" <e.voevodin@samsung.com>,
"Mark Langsdorf" <mark.langsdorf@calxeda.com>,
"Peter Crosthwaite" <peter.crosthwaite@petalogix.com>,
"Jan Kiszka" <jan.kiszka@web.de>,
"Dmitry Solodkiy" <d.solodkiy@samsung.com>,
"Maksim Kozlov" <m.kozlov@samsung.com>,
"Andreas Färber" <afaerber@suse.de>,
"Paul Brook" <paul@codesourcery.com>
Subject: [Qemu-devel] [PATCH v5 30/43] arm hw/: Don't use CPUState
Date: Wed, 14 Mar 2012 22:42:43 +0100 [thread overview]
Message-ID: <1331761376-20362-31-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1331761376-20362-1-git-send-email-afaerber@suse.de>
Scripted conversion:
for file in hw/arm-misc.h hw/arm_boot.c hw/arm_pic.c hw/armv7m.c hw/exynos4210.h hw/highbank.c hw/integratorcp.c hw/musicpal.c hw/omap.h hw/pxa.h hw/pxa2xx_gpio.c hw/pxa2xx_pic.c hw/realview.c hw/strongarm.h hw/versatilepb.c hw/vexpress.c hw/xilinx_zynq.c ; do
sed -i "s/CPUState/CPUARMState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
---
hw/arm-misc.h | 8 ++++----
hw/arm_boot.c | 8 ++++----
hw/arm_pic.c | 4 ++--
hw/armv7m.c | 4 ++--
hw/exynos4210.h | 2 +-
hw/highbank.c | 8 ++++----
hw/integratorcp.c | 2 +-
hw/musicpal.c | 2 +-
hw/omap.h | 2 +-
hw/pxa.h | 6 +++---
hw/pxa2xx_gpio.c | 4 ++--
hw/pxa2xx_pic.c | 4 ++--
hw/realview.c | 2 +-
hw/strongarm.h | 2 +-
hw/versatilepb.c | 2 +-
hw/vexpress.c | 4 ++--
hw/xilinx_zynq.c | 2 +-
17 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index 734bd82..2f46e21 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -16,7 +16,7 @@
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
-qemu_irq *arm_pic_init_cpu(CPUState *env);
+qemu_irq *arm_pic_init_cpu(CPUARMState *env);
/* armv7m.c */
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
@@ -50,16 +50,16 @@ struct arm_boot_info {
* perform any necessary CPU reset handling and set the PC for thei
* secondary CPUs to point at this boot blob.
*/
- void (*write_secondary_boot)(CPUState *env,
+ void (*write_secondary_boot)(CPUARMState *env,
const struct arm_boot_info *info);
- void (*secondary_cpu_reset_hook)(CPUState *env,
+ void (*secondary_cpu_reset_hook)(CPUARMState *env,
const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
target_phys_addr_t initrd_size;
target_phys_addr_t entry;
};
-void arm_load_kernel(CPUState *env, struct arm_boot_info *info);
+void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info);
/* Multiplication factor to convert from system clock ticks to qemu timer
ticks. */
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index 23b3f0a..7447f5c 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -59,7 +59,7 @@ static uint32_t smpboot[] = {
0 /* bootreg: Boot register address is held here */
};
-static void default_write_secondary(CPUState *env,
+static void default_write_secondary(CPUARMState *env,
const struct arm_boot_info *info)
{
int n;
@@ -72,7 +72,7 @@ static void default_write_secondary(CPUState *env,
info->smp_loader_start);
}
-static void default_reset_secondary(CPUState *env,
+static void default_reset_secondary(CPUARMState *env,
const struct arm_boot_info *info)
{
stl_phys_notdirty(info->smp_bootreg_addr, 0);
@@ -274,7 +274,7 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
static void do_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUARMState *env = opaque;
const struct arm_boot_info *info = env->boot_info;
cpu_state_reset(env);
@@ -300,7 +300,7 @@ static void do_cpu_reset(void *opaque)
}
}
-void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
+void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
{
int kernel_size;
int initrd_size;
diff --git a/hw/arm_pic.c b/hw/arm_pic.c
index a2e8a73..1094965 100644
--- a/hw/arm_pic.c
+++ b/hw/arm_pic.c
@@ -13,7 +13,7 @@
/* Input 0 is IRQ and input 1 is FIQ. */
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
- CPUState *env = (CPUState *)opaque;
+ CPUARMState *env = (CPUARMState *)opaque;
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level)
@@ -32,7 +32,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
}
}
-qemu_irq *arm_pic_init_cpu(CPUState *env)
+qemu_irq *arm_pic_init_cpu(CPUARMState *env)
{
return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
}
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 9cf96f4..4aac076 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
static void armv7m_reset(void *opaque)
{
- cpu_state_reset((CPUState *)opaque);
+ cpu_state_reset((CPUARMState *)opaque);
}
/* Init CPU and memory for a v7-M based board.
@@ -160,7 +160,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUARMState *env;
DeviceState *nvic;
/* FIXME: make this local state. */
static qemu_irq pic[64];
diff --git a/hw/exynos4210.h b/hw/exynos4210.h
index e7522f8..c112e03 100644
--- a/hw/exynos4210.h
+++ b/hw/exynos4210.h
@@ -83,7 +83,7 @@ typedef struct Exynos4210Irq {
} Exynos4210Irq;
typedef struct Exynos4210State {
- CPUState * env[EXYNOS4210_NCPUS];
+ CPUARMState * env[EXYNOS4210_NCPUS];
Exynos4210Irq irqs;
qemu_irq *irq_table;
diff --git a/hw/highbank.c b/hw/highbank.c
index 489c00e..906eed5 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -37,12 +37,12 @@
/* Board init. */
static void highbank_cpu_reset(void *opaque)
{
- CPUState *env = opaque;
+ CPUARMState *env = opaque;
env->cp15.c15_config_base_address = GIC_BASE_ADDR;
}
-static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
+static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
int n;
uint32_t smpboot[] = {
@@ -66,7 +66,7 @@ static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}
-static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)
+static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
switch (info->nb_cpus) {
case 4:
@@ -196,7 +196,7 @@ static void highbank_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq *irqp;
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 5b06c81..9bdb9e6 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -443,7 +443,7 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUARMState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
diff --git a/hw/musicpal.c b/hw/musicpal.c
index 187a1ae..c9f845a 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -1513,7 +1513,7 @@ static void musicpal_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env;
+ CPUARMState *env;
qemu_irq *cpu_pic;
qemu_irq pic[32];
DeviceState *dev;
diff --git a/hw/omap.h b/hw/omap.h
index 60fa34c..63ef847 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -813,7 +813,7 @@ struct omap_mpu_state_s {
omap3630,
} mpu_model;
- CPUState *env;
+ CPUARMState *env;
qemu_irq *drq;
diff --git a/hw/pxa.h b/hw/pxa.h
index e778739..025be34 100644
--- a/hw/pxa.h
+++ b/hw/pxa.h
@@ -65,11 +65,11 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
+DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env);
/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
- CPUState *env, DeviceState *pic, int lines);
+ CPUARMState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
@@ -122,7 +122,7 @@ typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;
typedef struct {
- CPUState *env;
+ CPUARMState *env;
DeviceState *pic;
qemu_irq reset;
MemoryRegion sdram;
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index d5f5716..09a408b 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -20,7 +20,7 @@ struct PXA2xxGPIOInfo {
qemu_irq irq0, irq1, irqX;
int lines;
int ncpu;
- CPUState *cpu_env;
+ CPUARMState *cpu_env;
/* XXX: GNU C vectors are more suitable */
uint32_t ilevel[PXA2XX_GPIO_BANKS];
@@ -249,7 +249,7 @@ static const MemoryRegionOps pxa_gpio_ops = {
};
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
- CPUState *env, DeviceState *pic, int lines)
+ CPUARMState *env, DeviceState *pic, int lines)
{
DeviceState *dev;
diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index 6b2bdb0..a806b80 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -34,7 +34,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
- CPUState *cpu_env;
+ CPUARMState *cpu_env;
uint32_t int_enabled[2];
uint32_t int_pending[2];
uint32_t is_fiq[2];
@@ -245,7 +245,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
return 0;
}
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
+DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env)
{
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
diff --git a/hw/realview.c b/hw/realview.c
index 50ea67c..cf55204 100644
--- a/hw/realview.c
+++ b/hw/realview.c
@@ -128,7 +128,7 @@ static void realview_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
enum realview_board_type board_type)
{
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
diff --git a/hw/strongarm.h b/hw/strongarm.h
index 684f61b..02acac3 100644
--- a/hw/strongarm.h
+++ b/hw/strongarm.h
@@ -53,7 +53,7 @@ enum {
};
typedef struct {
- CPUState *env;
+ CPUARMState *env;
MemoryRegion sdram;
DeviceState *pic;
DeviceState *gpio;
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index c1687a5..25afb1e 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -167,7 +167,7 @@ static void versatile_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
int board_id)
{
- CPUState *env;
+ CPUARMState *env;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_pic;
diff --git a/hw/vexpress.c b/hw/vexpress.c
index b9aafec..18d87ac 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -159,7 +159,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
const char *cpu_model,
qemu_irq *pic, uint32_t *proc_id)
{
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *lowram = g_new(MemoryRegion, 1);
@@ -259,7 +259,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
qemu_irq *pic, uint32_t *proc_id)
{
int n;
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index ea13e8c..7290c64 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -50,7 +50,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- CPUState *env = NULL;
+ CPUARMState *env = NULL;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
--
1.7.7
next prev parent reply other threads:[~2012-03-14 21:43 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-14 21:42 [Qemu-devel] [PULL] QOM CPUState v5 Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 01/43] PPC: 405: Use proper CPU reset Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 02/43] Rename cpu_reset() to cpu_state_reset() Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 03/43] monitor: Don't access registers through CPUState Andreas Färber
2012-03-15 16:15 ` Lluís Vilanova
2012-03-15 18:12 ` Andreas Färber
2012-03-15 21:35 ` Lluís Vilanova
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 04/43] monitor: Avoid CPUState in read/write functions Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 05/43] target-lm32/microblaze: Typedef struct CPU{MB, LM32}State Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 06/43] target-sparc: Typedef struct CPUSPARCState early Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 07/43] target-unicore32: Rename to CPUUniCore32State Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 08/43] hw/mc146818: Drop unneeded #includes Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 09/43] linux-user: Don't overuse CPUState Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 10/43] darwin-user: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 11/43] bsd-user: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 12/43] target-alpha: " Andreas Färber
2012-03-17 19:20 ` Richard Henderson
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 13/43] target-arm: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 14/43] target-cris: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 15/43] target-i386: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 16/43] target-lm32: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 17/43] target-m68k: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 18/43] target-microblaze: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 19/43] target-mips: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 20/43] target-ppc: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 21/43] target-s390x: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 22/43] target-sh4: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 23/43] target-sparc: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 24/43] target-unicore32: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 25/43] target-xtensa: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 26/43] arm-semi: Don't use CPUState Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 27/43] m68k-semi: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 28/43] xtensa-semi: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 29/43] alpha hw/: " Andreas Färber
2012-03-14 21:42 ` Andreas Färber [this message]
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 31/43] cris " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 32/43] i386 " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 33/43] lm32 " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 34/43] m68k " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 35/43] microblaze " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 36/43] mips " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 37/43] ppc " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 38/43] s390x " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 39/43] sh4 " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 40/43] sparc " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 41/43] xtensa " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 42/43] Rename CPUState -> CPUArchState Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 43/43] qom: Introduce CPU class Andreas Färber
2012-03-15 0:49 ` [Qemu-devel] [PULL] QOM CPUState v5 Anthony Liguori
2012-03-15 10:16 ` [Qemu-devel] [PULL] QOM CPUState v5 - conflict resolution info Andreas Färber
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1331761376-20362-31-git-send-email-afaerber@suse.de \
--to=afaerber@suse.de \
--cc=d.solodkiy@samsung.com \
--cc=e.voevodin@samsung.com \
--cc=i.mitsyanko@samsung.com \
--cc=jan.kiszka@web.de \
--cc=m.kozlov@samsung.com \
--cc=mark.langsdorf@calxeda.com \
--cc=paul@codesourcery.com \
--cc=peter.crosthwaite@petalogix.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).