From: "Andreas Färber" <afaerber@suse.de>
To: qemu-devel@nongnu.org
Cc: "Andreas Färber" <afaerber@suse.de>
Subject: [Qemu-devel] [PATCH v5 04/43] monitor: Avoid CPUState in read/write functions
Date: Wed, 14 Mar 2012 22:42:17 +0100 [thread overview]
Message-ID: <1331761376-20362-5-git-send-email-afaerber@suse.de> (raw)
In-Reply-To: <1331761376-20362-1-git-send-email-afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
---
gdbstub.c | 56 ++++++++++++++++++++++++++++----------------------------
1 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index ef95ac2..b5ec362 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -533,7 +533,7 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
#define IDX_XMM_REGS (IDX_FP_REGS + 16)
#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
if (n < CPU_NB_REGS) {
if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
@@ -590,7 +590,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
+static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
{
uint16_t selector = ldl_p(mem_buf);
@@ -615,7 +615,7 @@ static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
return 4;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -703,7 +703,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GDB_CORE_XML "power-core.xml"
#endif
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
/* gprs */
@@ -740,7 +740,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
/* gprs */
@@ -801,7 +801,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GET_REGA(val) GET_REGL(val)
#endif
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* g0..g7 */
@@ -860,7 +860,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
{
#if defined(TARGET_ABI32)
abi_ulong tmp;
@@ -944,7 +944,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 26
#define GDB_CORE_XML "arm-core.xml"
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
{
if (n < 16) {
/* Core integer register. */
@@ -971,7 +971,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1014,7 +1014,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define GDB_CORE_XML "cf-core.xml"
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
/* D0-D7 */
@@ -1033,7 +1033,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1058,7 +1058,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 73
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REGL(env->active_tc.gpr[n]);
@@ -1104,7 +1104,7 @@ static unsigned int ieee_rm[] =
#define RESTORE_ROUNDING_MODE \
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
{
target_ulong tmp;
@@ -1163,7 +1163,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 59
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
if (n < 8) {
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
@@ -1197,7 +1197,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1244,7 +1244,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS (32 + 5)
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->regs[n]);
@@ -1254,7 +1254,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1275,7 +1275,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 49
static int
-read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
+read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
{
if (n < 15) {
GET_REG32(env->regs[n]);
@@ -1307,7 +1307,7 @@ read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
{
uint8_t srs;
@@ -1337,7 +1337,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1370,7 +1370,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS 67
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
{
uint64_t val;
CPU_DoubleU d;
@@ -1404,7 +1404,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
GET_REGL(val);
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
{
target_ulong tmp = ldtul_p(mem_buf);
CPU_DoubleU d;
@@ -1440,7 +1440,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS S390_NUM_TOTAL_REGS
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
{
switch (n) {
case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
@@ -1464,7 +1464,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
{
target_ulong tmpl;
uint32_t tmp32;
@@ -1494,7 +1494,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#include "hw/lm32_pic.h"
#define NUM_CORE_REGS (32 + 7)
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->regs[n]);
@@ -1527,7 +1527,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
return 0;
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -1573,7 +1573,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
#define num_g_regs NUM_CORE_REGS
-static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
@@ -1610,7 +1610,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
}
}
-static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
+static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
--
1.7.7
next prev parent reply other threads:[~2012-03-14 21:43 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-14 21:42 [Qemu-devel] [PULL] QOM CPUState v5 Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 01/43] PPC: 405: Use proper CPU reset Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 02/43] Rename cpu_reset() to cpu_state_reset() Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 03/43] monitor: Don't access registers through CPUState Andreas Färber
2012-03-15 16:15 ` Lluís Vilanova
2012-03-15 18:12 ` Andreas Färber
2012-03-15 21:35 ` Lluís Vilanova
2012-03-14 21:42 ` Andreas Färber [this message]
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 05/43] target-lm32/microblaze: Typedef struct CPU{MB, LM32}State Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 06/43] target-sparc: Typedef struct CPUSPARCState early Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 07/43] target-unicore32: Rename to CPUUniCore32State Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 08/43] hw/mc146818: Drop unneeded #includes Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 09/43] linux-user: Don't overuse CPUState Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 10/43] darwin-user: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 11/43] bsd-user: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 12/43] target-alpha: " Andreas Färber
2012-03-17 19:20 ` Richard Henderson
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 13/43] target-arm: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 14/43] target-cris: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 15/43] target-i386: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 16/43] target-lm32: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 17/43] target-m68k: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 18/43] target-microblaze: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 19/43] target-mips: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 20/43] target-ppc: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 21/43] target-s390x: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 22/43] target-sh4: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 23/43] target-sparc: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 24/43] target-unicore32: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 25/43] target-xtensa: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 26/43] arm-semi: Don't use CPUState Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 27/43] m68k-semi: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 28/43] xtensa-semi: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 29/43] alpha hw/: " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 30/43] arm " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 31/43] cris " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 32/43] i386 " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 33/43] lm32 " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 34/43] m68k " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 35/43] microblaze " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 36/43] mips " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 37/43] ppc " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 38/43] s390x " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 39/43] sh4 " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 40/43] sparc " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 41/43] xtensa " Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 42/43] Rename CPUState -> CPUArchState Andreas Färber
2012-03-14 21:42 ` [Qemu-devel] [PATCH v5 43/43] qom: Introduce CPU class Andreas Färber
2012-03-15 0:49 ` [Qemu-devel] [PULL] QOM CPUState v5 Anthony Liguori
2012-03-15 10:16 ` [Qemu-devel] [PULL] QOM CPUState v5 - conflict resolution info Andreas Färber
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