[Qemu-devel] [PULL 0/3] target-arm queue

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Hi; this is a pullreq for my target-arm queue. Just three fairly
minor bug fixes this time. Please pull.

Thanks
-- PMM

The following changes since commit ae7d54d489540b49b7c13a7df7ddc220588a2ced:

  target-lm32/microblaze: Drop second CPU{LM32, MB}State typedef (2012-03-14 19:48:37 -0500)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Peter Maydell (3):
      target-arm: Fix typo in ARM946 cp15 c5 handling
      target-arm: Clear IT bits when taking exceptions in v7M
      target-arm: Decode SETEND correctly in Thumb

 target-arm/helper.c    |    5 ++-
 target-arm/translate.c |   63 ++++++++++++++++++++++++++++++-----------------
 2 files changed, 43 insertions(+), 25 deletions(-)

[Qemu-devel] [PATCH 1/3] target-arm: Fix typo in ARM946 cp15 c5 handling

[Peter Maydell]

Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling
(instruction access permission bits) that meant it would
return the data access permission bits by mistake.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8a08db8..4116fee 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2025,7 +2025,7 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
             return env->cp15.c5_data;
         case 1:
             if (arm_feature(env, ARM_FEATURE_MPU))
-                return simple_mpu_ap_bits(env->cp15.c5_data);
+                return simple_mpu_ap_bits(env->cp15.c5_insn);
             return env->cp15.c5_insn;
         case 2:
             if (!arm_feature(env, ARM_FEATURE_MPU))
-- 
1.7.1

[Qemu-devel] [PATCH 2/3] target-arm: Clear IT bits when taking exceptions in v7M

[Peter Maydell]

When taking an exception for an M profile core, we must clear
the IT bits. Since the IT bits are cached in env->condexec_bits
we must clear them there: writing the bits in env->uncached_cpsr
has no effect. (Reported as LP:944645.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4116fee..1314f23 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -877,7 +877,8 @@ static void do_interrupt_v7m(CPUARMState *env)
     v7m_push(env, env->regs[1]);
     v7m_push(env, env->regs[0]);
     switch_v7m_sp(env, 0);
-    env->uncached_cpsr &= ~CPSR_IT;
+    /* Clear IT bits */
+    env->condexec_bits = 0;
     env->regs[14] = lr;
     addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
     env->regs[15] = addr & 0xfffffffe;
-- 
1.7.1

[Qemu-devel] [PATCH 3/3] target-arm: Decode SETEND correctly in Thumb

[Peter Maydell]

Decode the SETEND instruction correctly in Thumb mode,
rather than accidentally treating it like CPS. We don't
support BE8 mode, but this change brings the Thumb mode
in to line with behaviour in ARM mode: 'SETEND BE' is
not supported and will provoke an UNDEF exception, but
'SETEND LE' is correctly handled as a no-op.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Daniel Forsgren <daniel.forsgren@enea.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
---
 target-arm/translate.c |   63 ++++++++++++++++++++++++++++++-----------------
 1 files changed, 40 insertions(+), 23 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 2709010..81725d1 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9704,32 +9704,49 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
             store_reg(s, rd, tmp);
             break;
 
-        case 6: /* cps */
-            ARCH(6);
-            if (IS_USER(s))
+        case 6:
+            switch ((insn >> 5) & 7) {
+            case 2:
+                /* setend */
+                ARCH(6);
+                if (insn & (1 << 3)) {
+                    /* BE8 mode not implemented.  */
+                    goto illegal_op;
+                }
                 break;
-            if (IS_M(env)) {
-                tmp = tcg_const_i32((insn & (1 << 4)) != 0);
-                /* FAULTMASK */
-                if (insn & 1) {
-                    addr = tcg_const_i32(19);
-                    gen_helper_v7m_msr(cpu_env, addr, tmp);
-                    tcg_temp_free_i32(addr);
+            case 3:
+                /* cps */
+                ARCH(6);
+                if (IS_USER(s)) {
+                    break;
                 }
-                /* PRIMASK */
-                if (insn & 2) {
-                    addr = tcg_const_i32(16);
-                    gen_helper_v7m_msr(cpu_env, addr, tmp);
-                    tcg_temp_free_i32(addr);
+                if (IS_M(env)) {
+                    tmp = tcg_const_i32((insn & (1 << 4)) != 0);
+                    /* FAULTMASK */
+                    if (insn & 1) {
+                        addr = tcg_const_i32(19);
+                        gen_helper_v7m_msr(cpu_env, addr, tmp);
+                        tcg_temp_free_i32(addr);
+                    }
+                    /* PRIMASK */
+                    if (insn & 2) {
+                        addr = tcg_const_i32(16);
+                        gen_helper_v7m_msr(cpu_env, addr, tmp);
+                        tcg_temp_free_i32(addr);
+                    }
+                    tcg_temp_free_i32(tmp);
+                    gen_lookup_tb(s);
+                } else {
+                    if (insn & (1 << 4)) {
+                        shift = CPSR_A | CPSR_I | CPSR_F;
+                    } else {
+                        shift = 0;
+                    }
+                    gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
                 }
-                tcg_temp_free_i32(tmp);
-                gen_lookup_tb(s);
-            } else {
-                if (insn & (1 << 4))
-                    shift = CPSR_A | CPSR_I | CPSR_F;
-                else
-                    shift = 0;
-                gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
+                break;
+            default:
+                goto undef;
             }
             break;
 
-- 
1.7.1

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Blue Swirl]

On Fri, Mar 16, 2012 at 18:21, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is a pullreq for my target-arm queue. Just three fairly
> minor bug fixes this time. Please pull.

Thanks, pulled.

> Thanks
> -- PMM
>
> The following changes since commit ae7d54d489540b49b7c13a7df7ddc220588a2ced:
>
>  target-lm32/microblaze: Drop second CPU{LM32, MB}State typedef (2012-03-14 19:48:37 -0500)
>
> are available in the git repository at:
>  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> Peter Maydell (3):
>      target-arm: Fix typo in ARM946 cp15 c5 handling
>      target-arm: Clear IT bits when taking exceptions in v7M
>      target-arm: Decode SETEND correctly in Thumb
>
>  target-arm/helper.c    |    5 ++-
>  target-arm/translate.c |   63 ++++++++++++++++++++++++++++++-----------------
>  2 files changed, 43 insertions(+), 25 deletions(-)