From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41963) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S8unx-0002L8-3L for qemu-devel@nongnu.org; Sat, 17 Mar 2012 10:40:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S8unt-000410-VD for qemu-devel@nongnu.org; Sat, 17 Mar 2012 10:40:24 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sat, 17 Mar 2012 15:39:45 +0100 Message-Id: <1331995186-18507-6-git-send-email-hpoussin@reactos.org> In-Reply-To: <1331995186-18507-1-git-send-email-hpoussin@reactos.org> References: <1331995186-18507-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 5/6] prep: add pc87312 Super I/O emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= This provides floppy and IDE controllers as well as serial and parallel p= orts. However, dynamic configuration of devices is not yet supported. Cc: Andreas F=C3=A4rber Signed-off-by: Herv=C3=A9 Poussineau --- Makefile.objs | 1 + hw/pc87312.c | 425 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++ 2 files changed, 426 insertions(+), 0 deletions(-) create mode 100644 hw/pc87312.c diff --git a/Makefile.objs b/Makefile.objs index 226b01d..232eed0 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -252,6 +252,7 @@ hw-obj-$(CONFIG_I8259) +=3D i8259_common.o i8259.o # PPC devices hw-obj-$(CONFIG_PREP_PCI) +=3D prep_pci.o hw-obj-$(CONFIG_I82378) +=3D i82378.o +hw-obj-$(CONFIG_PC87312) +=3D pc87312.o # Mac shared devices hw-obj-$(CONFIG_MACIO) +=3D macio.o hw-obj-$(CONFIG_CUDA) +=3D cuda.o diff --git a/hw/pc87312.c b/hw/pc87312.c new file mode 100644 index 0000000..1e28dbd --- /dev/null +++ b/hw/pc87312.c @@ -0,0 +1,425 @@ +/* + * QEMU National Semiconductor PC87312 (Super I/O) + * + * Copyright (c) 2010-2012 Herve Poussineau + * + * Permission is hereby granted, free of charge, to any person obtaining= a copy + * of this software and associated documentation files (the "Software"),= to deal + * in the Software without restriction, including without limitation the= rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or = sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be includ= ed in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRE= SS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILI= TY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHA= LL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR = OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISI= NG FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALING= S IN + * THE SOFTWARE. + */ + +#include "isa.h" +#include "fdc.h" +#include "ide.h" + +//#define DEBUG_PC87312 + +#ifdef DEBUG_PC87312 +#define DPRINTF(fmt, ...) \ +do { fprintf(stderr, "pc87312: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) \ +do {} while (0) +#endif + +#define BADF(fmt, ...) \ +do { fprintf(stderr, "pc87312 ERROR: " fmt , ## __VA_ARGS__); } while (0= ) + +#define REG_FER 0 +#define REG_FAR 1 +#define REG_PTR 2 + +#define FER regs[REG_FER] +#define FAR regs[REG_FAR] +#define PTR regs[REG_PTR] + +#define FER_PARALLEL_EN 0x01 +#define FER_UART1_EN 0x02 +#define FER_UART2_EN 0x04 +#define FER_FDC_EN 0x08 +#define FER_FDC_4 0x10 +#define FER_FDC_ADDR 0x20 +#define FER_IDE_EN 0x40 +#define FER_IDE_ADDR 0x80 + +#define FAR_PARALLEL_ADDR 0x03 +#define FAR_UART1_ADDR 0x0C +#define FAR_UART2_ADDR 0x30 +#define FAR_UART_3_4 0xC0 + +#define PTR_POWER_DOWN 0x01 +#define PTR_CLOCK_DOWN 0x02 +#define PTR_PWDN 0x04 +#define PTR_IRQ_5_7 0x08 +#define PTR_UART1_TEST 0x10 +#define PTR_UART2_TEST 0x20 +#define PTR_LOCK_CONF 0x40 +#define PTR_EPP_MODE 0x80 + +typedef struct PC87312State { + ISADevice dev; + uint32_t iobase; + + uint8_t config; /* initial configuration */ + + struct { + DeviceState *dev; + CharDriverState *chr; + } parallel; + + struct { + DeviceState *dev; + CharDriverState *chr; + } uart[2]; + + struct { + DeviceState *dev; + BlockDriverState *drive[2]; + uint32_t base; + } fdc; + + struct { + DeviceState *dev; + uint32_t base; + } ide; + + uint8_t read_id_step; + uint8_t selected_index; + + uint8_t regs[3]; +} PC87312State; + + +/* Parallel port */ + +static inline bool is_parallel_enabled(PC87312State *s) +{ + return s->FER & FER_PARALLEL_EN; +} + +static const uint32_t parallel_base[] =3D { 0x378, 0x3bc, 0x278, 0x00 }; + +static inline uint32_t get_parallel_iobase(PC87312State *s) +{ + return parallel_base[s->FAR & FAR_PARALLEL_ADDR]; +} + +static const uint32_t parallel_irq[] =3D { 5, 7, 5, 0 }; + +static inline uint32_t get_parallel_irq(PC87312State *s) +{ + int idx; + idx =3D (s->FAR & FAR_PARALLEL_ADDR); + if (idx =3D=3D 0) { + return (s->PTR & PTR_IRQ_5_7) ? 7 : 5; + } else { + return parallel_irq[idx]; + } +} + +static inline bool is_parallel_epp(PC87312State *s) +{ + return s->PTR & PTR_EPP_MODE; +} + + +/* UARTs */ + +static const uint32_t uart_base[2][4] =3D { + { 0x3e8, 0x338, 0x2e8, 0x220 }, + { 0x2e8, 0x238, 0x2e0, 0x228 } +}; + +static inline uint32_t get_uart_iobase(PC87312State *s, int i) +{ + int idx; + idx =3D (s->FAR >> (2 * i + 2)) & 0x3; + if (idx =3D=3D 0) { + return 0x3f8; + } else if (idx =3D=3D 1) { + return 0x2f8; + } else { + return uart_base[idx & 1][(s->FAR & FAR_UART_3_4) >> 6]; + } +} + +static inline uint32_t get_uart_irq(PC87312State *s, int i) +{ + int idx; + idx =3D (s->FAR >> (2 * i + 2)) & 0x3; + return (idx & 1) ? 3 : 4; +} + +static inline bool is_uart_enabled(PC87312State *s, int i) +{ + return s->FER & (FER_UART1_EN << i); +} + + +/* Floppy controller */ + +static inline bool is_fdc_enabled(PC87312State *s) +{ + return s->FER & FER_FDC_EN; +} + +static inline uint32_t get_fdc_iobase(PC87312State *s) +{ + return (s->FER & FER_FDC_ADDR) ? 0x370 : 0x3f0; +} + + +/* IDE controller */ + +static inline bool is_ide_enabled(PC87312State *s) +{ + return s->FER & FER_IDE_EN; +} + +static inline uint32_t get_ide_iobase(PC87312State *s) +{ + return (s->FER & FER_IDE_ADDR) ? 0x170 : 0x1f0; +} + + +static void reconfigure_devices(PC87312State *s) +{ + error_report("pc87312: unsupported device reconfiguration (%02x %02x= %02x)", + s->FER, s->FAR, s->PTR); +} + +static void pc87312_soft_reset(PC87312State *s) +{ + static const uint8_t fer_init[] =3D { + 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b, + 0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f, + 0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07, + 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00, + }; + static const uint8_t far_init[] =3D { + 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01, + 0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24, + 0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24, + 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10, + }; + static const uint8_t ptr_init[] =3D { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + }; + + s->read_id_step =3D 0; + s->selected_index =3D REG_FER; + + s->FER =3D fer_init[s->config & 0x1f]; + s->FAR =3D far_init[s->config & 0x1f]; + s->PTR =3D ptr_init[s->config & 0x1f]; +} + +static void pc87312_hard_reset(PC87312State *s) +{ + pc87312_soft_reset(s); +} + +static void pc87312_ioport_write(void *opaque, uint32_t addr, uint32_t v= al) +{ + PC87312State *s =3D opaque; + + DPRINTF("%s: write %x at %x\n", __func__, val, addr); + + if ((addr & 1) =3D=3D 0) { + /* Index register */ + s->read_id_step =3D 2; + s->selected_index =3D val; + } else { + /* Data register */ + if (s->selected_index < 3) { + s->regs[s->selected_index] =3D val; + reconfigure_devices(s); + } + } +} + +static uint32_t pc87312_ioport_read(void *opaque, uint32_t addr) +{ + PC87312State *s =3D opaque; + uint32_t val; + + if ((addr & 1) =3D=3D 0) { + /* Index register */ + if (s->read_id_step++ =3D=3D 0) { + val =3D 0x88; + } else if (s->read_id_step++ =3D=3D 1) { + val =3D 0; + } else { + val =3D s->selected_index; + } + } else { + /* Data register */ + if (s->selected_index < 3) { + val =3D s->regs[s->selected_index]; + } else { + /* Invalid selected index */ + val =3D 0; + } + } + + DPRINTF("%s: read %x at %x\n", __func__, val, addr); + return val; +} + +static int pc87312_post_load(void *opaque, int version_id) +{ + PC87312State *s =3D opaque; + reconfigure_devices(s); + return 0; +} + +static void pc87312_reset(DeviceState *d) +{ + PC87312State *s =3D container_of(d, PC87312State, dev.qdev); + pc87312_soft_reset(s); +} + +static int pc87312_init(ISADevice *dev) +{ + PC87312State *s; + ISADevice *isa; + ISABus *bus; + CharDriverState *chr; + BlockDriverState *bs; + int i; + + s =3D DO_UPCAST(PC87312State, dev, dev); + bus =3D isa_bus_from_device(dev); + pc87312_hard_reset(s); + + chr =3D s->parallel.chr; + if (s->parallel.chr !=3D NULL && is_parallel_enabled(s)) { + qemu_chr_add_handlers(chr, NULL, NULL, NULL, NULL); /* HACK */ + isa =3D isa_create(bus, "isa-parallel"); + qdev_prop_set_uint32(&isa->qdev, "index", 0); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_parallel_iobase(s= )); + qdev_prop_set_uint32(&isa->qdev, "irq", get_parallel_irq(s)); + qdev_prop_set_chr(&isa->qdev, "chardev", chr); + qdev_init_nofail(&isa->qdev); + s->parallel.dev =3D &isa->qdev; + DPRINTF("parallel: base 0x%x, irq %u\n", + get_parallel_iobase(s), get_parallel_irq(s)); + } + + for (i =3D 0; i < 2; i++) { + chr =3D s->uart[i].chr; + if (chr !=3D NULL && is_uart_enabled(s, i)) { + qemu_chr_add_handlers(chr, NULL, NULL, NULL, NULL); /* HACK = */ + isa =3D isa_create(bus, "isa-serial"); + qdev_prop_set_uint32(&isa->qdev, "index", i); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_uart_iobase(s= , i)); + qdev_prop_set_uint32(&isa->qdev, "irq", get_uart_irq(s, i)); + qdev_prop_set_chr(&isa->qdev, "chardev", chr); + qdev_init_nofail(&isa->qdev); + s->uart[i].dev =3D &isa->qdev; + DPRINTF("uart%d: base 0x%x, irq %u\n", i, + get_uart_iobase(s, i), + get_uart_irq(s, i)); + } + } + + if (is_fdc_enabled(s)) { + isa =3D isa_create(bus, "isa-fdc"); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_fdc_iobase(s)); + qdev_prop_set_uint32(&isa->qdev, "irq", 6); + bs =3D s->fdc.drive[0]; + if (bs !=3D NULL) { + bdrv_detach_dev(bs, bdrv_get_attached_dev(bs)); /* HACK */ + qdev_prop_set_drive_nofail(&isa->qdev, "driveA", bs); + } + bs =3D s->fdc.drive[1]; + if (bs !=3D NULL) { + bdrv_detach_dev(bs, bdrv_get_attached_dev(bs)); /* HACK */ + qdev_prop_set_drive_nofail(&isa->qdev, "driveB", bs); + } + qdev_init_nofail(&isa->qdev); + s->fdc.dev =3D &isa->qdev; + DPRINTF("fdc: base 0x%x\n", get_fdc_iobase(s)); + } + + if (is_ide_enabled(s)) { + isa =3D isa_create(bus, "isa-ide"); + qdev_prop_set_uint32(&isa->qdev, "iobase", get_ide_iobase(s)); + qdev_prop_set_uint32(&isa->qdev, "iobase2", get_ide_iobase(s) + = 0x206); + qdev_prop_set_uint32(&isa->qdev, "irq", 14); + qdev_init_nofail(&isa->qdev); + s->ide.dev =3D &isa->qdev; + DPRINTF("ide: base 0x%x\n", get_ide_iobase(s)); + } + + register_ioport_write(s->iobase, 2, 1, pc87312_ioport_write, s); + register_ioport_read(s->iobase, 2, 1, pc87312_ioport_read, s); + return 0; +} + +static const VMStateDescription vmstate_pc87312 =3D { + .name =3D "pc87312", + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D pc87312_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(read_id_step, PC87312State), + VMSTATE_UINT8(selected_index, PC87312State), + VMSTATE_UINT8_ARRAY(regs, PC87312State, 3), + VMSTATE_END_OF_LIST() + } +}; + +static Property pc87312_properties[] =3D { + DEFINE_PROP_HEX32("iobase", PC87312State, iobase, 0x398), + DEFINE_PROP_UINT8("config", PC87312State, config, 1), + DEFINE_PROP_CHR("parallel", PC87312State, parallel.chr), + DEFINE_PROP_CHR("uart1", PC87312State, uart[0].chr), + DEFINE_PROP_CHR("uart2", PC87312State, uart[1].chr), + DEFINE_PROP_DRIVE("floppyA", PC87312State, fdc.drive[0]), + DEFINE_PROP_DRIVE("floppyB", PC87312State, fdc.drive[1]), + DEFINE_PROP_END_OF_LIST() +}; + +static void pc87312_class_initfn(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ISADeviceClass *ic =3D ISA_DEVICE_CLASS(klass); + + ic->init =3D pc87312_init; + dc->reset =3D pc87312_reset; + dc->vmsd =3D &vmstate_pc87312; + dc->props =3D pc87312_properties; +} + +static TypeInfo pc87312_info =3D { + .name =3D "pc87312", + .parent =3D TYPE_ISA_DEVICE, + .instance_size =3D sizeof(PC87312State), + .class_init =3D pc87312_class_initfn, +}; + +static void pc87312_register_types(void) +{ + type_register_static(&pc87312_info); +} + +type_init(pc87312_register_types) + --=20 1.7.9.1