[Qemu-devel] [RFC PATCH 0/3] Move CPU model config file to /usr/share

[Qemu-devel] [RFC PATCH 0/3] Move CPU model config file to /usr/share

[Eduardo Habkost]

This is a RFC, but I really want to include this on Qemu 1.1.

This will allow libvirt to reuse our CPU defs starting on Qemu 1.1, and will
give us some freedom to change the syntax and semantics of the cpudef sections,
as long as we keep the config file at the same place.

Making this change earlier will benefit users that use Qemu directly but simply
want to use the default CPU models (they won't have to update their config
files on /etc once we change the way cpudefs work), and libvirt, that will
finally be able to reuse the existing CPU models.

This series should be applied on top of both the "./configure --confdir" and
the "-readconfig fd=<fd>" series I submitted earlier today.

Eduardo Habkost (3):
  move list of default config files to qemu-config-arch.c
  implement -readconfig help=defconfig option
  move cpudef config sections to /usr/share/qemu/cpudefs-x86_64.conf

 Makefile                              |    2 +
 arch_init.c                           |    1 -
 arch_init.h                           |    2 -
 qemu-config-arch.c                    |   68 +++++++++++++++++-
 qemu-config-arch.h                    |    4 +
 sysconfigs/target/cpudefs-x86_64.conf |  127 ++++++++++++++++++++++++++++++++
 sysconfigs/target/target-x86_64.conf  |  128 ---------------------------------
 vl.c                                  |   12 +---
 8 files changed, 203 insertions(+), 141 deletions(-)
 create mode 100644 sysconfigs/target/cpudefs-x86_64.conf

-- 
1.7.3.2

[Qemu-devel] [RFC PATCH 1/3] move list of default config files to qemu-config-arch.c

[Eduardo Habkost]

Move the list to an array, with a "type" field to identify the config
file purpose/type.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 arch_init.c        |    1 -
 arch_init.h        |    2 --
 qemu-config-arch.c |   36 ++++++++++++++++++++++++++++++++++++
 qemu-config-arch.h |    4 ++++
 vl.c               |   12 +++---------
 5 files changed, 43 insertions(+), 12 deletions(-)

diff --git a/arch_init.c b/arch_init.c
index a95ef49..56b2147 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -54,7 +54,6 @@ int graphic_height = 600;
 int graphic_depth = 15;
 #endif
 
-const char arch_config_name[] = CONFIG_QEMU_CONFDIR "/target-" TARGET_ARCH ".conf";
 
 #if defined(TARGET_ALPHA)
 #define QEMU_ARCH QEMU_ARCH_ALPHA
diff --git a/arch_init.h b/arch_init.h
index 828256c..c7cb94a 100644
--- a/arch_init.h
+++ b/arch_init.h
@@ -1,8 +1,6 @@
 #ifndef QEMU_ARCH_INIT_H
 #define QEMU_ARCH_INIT_H
 
-extern const char arch_config_name[];
-
 enum {
     QEMU_ARCH_ALL = -1,
     QEMU_ARCH_ALPHA = 1,
diff --git a/qemu-config-arch.c b/qemu-config-arch.c
index ee5d515..83a0c89 100644
--- a/qemu-config-arch.c
+++ b/qemu-config-arch.c
@@ -45,6 +45,30 @@ static QemuOptsList qemu_readconfig_opts = {
     },
 };
 
+#define MAIN_CONFIG_NAME (CONFIG_QEMU_CONFDIR "/qemu.conf")
+#define ARCH_CONFIG_NAME (CONFIG_QEMU_CONFDIR "/target-" TARGET_ARCH ".conf")
+
+/* List of default config files
+ */
+struct DefaultConfigFile {
+    /* Identifier to the default config file.
+     */
+    const char *type;
+    /* Config file path
+     */
+    const char *path;
+};
+
+static struct DefaultConfigFile arch_default_configs[] = {
+    /* user-editable config files from /etc: */
+    /* Main, generic config file: */
+    {"main", MAIN_CONFIG_NAME},
+    /* Arch-specific config file: */
+    {"arch", ARCH_CONFIG_NAME},
+
+    /* end of list */
+    {NULL, NULL},
+};
 
 /* Read Qemu config file based on parsed QemuOpts object
  *
@@ -84,3 +108,15 @@ int qemu_read_config_arg(const char *arg)
     qemu_opts_del(opts);
     return r;
 }
+
+int qemu_read_default_configs(void)
+{
+    const struct DefaultConfigFile *cfg;
+    for (cfg = arch_default_configs; cfg->path; cfg++) {
+        int ret = qemu_read_config_filename(cfg->path);
+        if (ret < 0 && ret != -ENOENT) {
+            return ret;
+        }
+    }
+    return 0;
+}
diff --git a/qemu-config-arch.h b/qemu-config-arch.h
index 3a9943d..289ea59 100644
--- a/qemu-config-arch.h
+++ b/qemu-config-arch.h
@@ -12,4 +12,8 @@
  */
 int qemu_read_config_arg(const char *arg);
 
+/* Read default config files for the architecture
+ */
+int qemu_read_default_configs(void);
+
 #endif /* QEMU_CONFIG_ARCH_H */
diff --git a/vl.c b/vl.c
index 26e6738..2ef172b 100644
--- a/vl.c
+++ b/vl.c
@@ -2350,15 +2350,9 @@ int main(int argc, char **argv, char **envp)
     }
 
     if (defconfig) {
-        int ret;
-
-        ret = qemu_read_config_filename(CONFIG_QEMU_CONFDIR "/qemu.conf");
-        if (ret < 0 && ret != -ENOENT) {
-            exit(1);
-        }
-
-        ret = qemu_read_config_filename(arch_config_name);
-        if (ret < 0 && ret != -ENOENT) {
+        int ret = qemu_read_default_configs();
+        if (ret < 0) {
+            fprintf(stderr, "error loading default config files: %s", strerror(ret));
             exit(1);
         }
     }
-- 
1.7.3.2

[Qemu-devel] [RFC PATCH 2/3] implement -readconfig help=defconfig option

[Eduardo Habkost]

This method will list the paths of all default config files.

This is where the placement of qemu_read_config_arg() on
qemu-config-arch.c becomes necessary: we have to use the list of config
files to implement the new help option.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 qemu-config-arch.c |   27 ++++++++++++++++++++++++++-
 1 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/qemu-config-arch.c b/qemu-config-arch.c
index 83a0c89..832f0b0 100644
--- a/qemu-config-arch.c
+++ b/qemu-config-arch.c
@@ -41,6 +41,10 @@ static QemuOptsList qemu_readconfig_opts = {
             .name = "fd",
             .type = QEMU_OPT_NUMBER,
         },
+        {
+            .name = "help",
+            .type = QEMU_OPT_STRING,
+        },
         { /*End of list */ }
     },
 };
@@ -70,6 +74,22 @@ static struct DefaultConfigFile arch_default_configs[] = {
     {NULL, NULL},
 };
 
+/* print -readconfig help information
+ */
+static void readconfig_help(const char *arg)
+{
+    if (!strcmp(arg, "defconfig")) {
+        const struct DefaultConfigFile *cfg;
+        printf("Default config files:\n");
+        for (cfg = arch_default_configs; cfg->path; cfg++) {
+            printf("\t%s:\t%s\n", cfg->type, cfg->path);
+        }
+    } else {
+        fprintf(stderr, "Invalid readconfig help option: %s\n", arg);
+        exit(1);
+    }
+}
+
 /* Read Qemu config file based on parsed QemuOpts object
  *
  * Returns 0 on success, -errno on failure.
@@ -79,12 +99,17 @@ static int qemu_read_config_opts(QemuOpts *opts)
     int fd = -1;
     uint64_t fd_arg = qemu_opt_get_number(opts, "fd", (uint64_t)-1);
     const char *path = qemu_opt_get(opts, "path");
+    const char *help = qemu_opt_get(opts, "help");
+
 
     if (fd_arg != (uint64_t)-1) {
         fd = fd_arg;
     }
 
-    if (path) {
+    if (help) {
+        readconfig_help(help);
+        exit(0);
+    } else if (path) {
         return qemu_read_config_filename(path);
     } else if (fd >= 0) {
         return qemu_read_config_fd(fd);
-- 
1.7.3.2

[Qemu-devel] [RFC PATCH 3/3] move cpudef config sections to /usr/share/qemu/cpudefs-x86_64.conf

[Eduardo Habkost]

Motivations are:

1) Make the cpudefs reusable by the managment system if it wants to, so
it doesn't need to write cpudefs from scratch. Putting them on
/usr/share lets management reuse them without being affected by user
configuration on /etc.

I expect libvirt to do something equivalent to:
  $ cpuconf=$(qemu-system-x86_64 -readconfig help=defconfig | grep cpudefs: | cut -f3)
  $ qemu-system-x86_64 -nodefconfig -readconfig path=$cpuconf [...]

Note that '-readconfig help=defconfig' is just an example. A more
machine-friendly querying mechanism may be provided later.

2) We need to be able to deploy fixes to existing CPU definitions if
necessary, but to make that possible, the cpu definitions shouldn't be
copied and edited directly, but extended on config files on /etc (or on
the command-line) if necessary.

Note that the syntax or semantics of the cpudef section may change in
the future. This patch will make sure management systems can reuse the
cpudefs today using -readconfig, without worrying about how the cpudef
config syntax works.

As agreed on previous discussions, -nodefconfig will disable the loading
of this file, as expected.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 Makefile                              |    2 +
 qemu-config-arch.c                    |    5 ++
 sysconfigs/target/cpudefs-x86_64.conf |  127 ++++++++++++++++++++++++++++++++
 sysconfigs/target/target-x86_64.conf  |  128 ---------------------------------
 4 files changed, 134 insertions(+), 128 deletions(-)
 create mode 100644 sysconfigs/target/cpudefs-x86_64.conf

diff --git a/Makefile b/Makefile
index 9d583c4..876a5c9 100644
--- a/Makefile
+++ b/Makefile
@@ -281,6 +281,8 @@ endif
 install-sysconfig:
 	$(INSTALL_DIR) "$(DESTDIR)$(confdir)"
 	$(INSTALL_DATA) $(SRC_PATH)/sysconfigs/target/target-x86_64.conf "$(DESTDIR)$(confdir)"
+	$(INSTALL_DIR) "$(DESTDIR)$(datadir)"
+	$(INSTALL_DATA) "$(SRC_PATH)/sysconfigs/target/cpudefs-x86_64.conf" "$(DESTDIR)$(datadir)"
 
 install: all $(if $(BUILD_DOCS),install-doc) install-sysconfig
 	$(INSTALL_DIR) "$(DESTDIR)$(bindir)"
diff --git a/qemu-config-arch.c b/qemu-config-arch.c
index 832f0b0..95e9e77 100644
--- a/qemu-config-arch.c
+++ b/qemu-config-arch.c
@@ -51,6 +51,7 @@ static QemuOptsList qemu_readconfig_opts = {
 
 #define MAIN_CONFIG_NAME (CONFIG_QEMU_CONFDIR "/qemu.conf")
 #define ARCH_CONFIG_NAME (CONFIG_QEMU_CONFDIR "/target-" TARGET_ARCH ".conf")
+#define CPUDEFS_CONFIG_NAME (CONFIG_QEMU_DATADIR "/cpudefs-" TARGET_ARCH ".conf")
 
 /* List of default config files
  */
@@ -64,6 +65,10 @@ struct DefaultConfigFile {
 };
 
 static struct DefaultConfigFile arch_default_configs[] = {
+    /* not commonly edited config files with defaults, from /usr/share: */
+    /* CPU models: */
+    {"cpudefs", CPUDEFS_CONFIG_NAME},
+
     /* user-editable config files from /etc: */
     /* Main, generic config file: */
     {"main", MAIN_CONFIG_NAME},
diff --git a/sysconfigs/target/cpudefs-x86_64.conf b/sysconfigs/target/cpudefs-x86_64.conf
new file mode 100644
index 0000000..1aa498d
--- /dev/null
+++ b/sysconfigs/target/cpudefs-x86_64.conf
@@ -0,0 +1,127 @@
+# x86 CPU MODELS
+
+[cpudef]
+   name = "Conroe"
+   level = "2"
+   vendor = "GenuineIntel"
+   family = "6"
+   model = "2"
+   stepping = "3"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "ssse3 sse3"
+   extfeature_edx = "i64 xd syscall"
+   extfeature_ecx = "lahf_lm"
+   xlevel = "0x8000000A"
+   model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
+
+[cpudef]
+   name = "Penryn"
+   level = "2"
+   vendor = "GenuineIntel"
+   family = "6"
+   model = "2"
+   stepping = "3"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "sse4.1 cx16 ssse3 sse3"
+   extfeature_edx = "i64 xd syscall"
+   extfeature_ecx = "lahf_lm"
+   xlevel = "0x8000000A"
+   model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
+
+[cpudef]
+   name = "Nehalem"
+   level = "2"
+   vendor = "GenuineIntel"
+   family = "6"
+   model = "2"
+   stepping = "3"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
+   extfeature_edx = "i64 syscall xd"
+   extfeature_ecx = "lahf_lm"
+   xlevel = "0x8000000A"
+   model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
+
+[cpudef]
+   name = "Westmere"
+   level = "11"
+   vendor = "GenuineIntel"
+   family = "6"
+   model = "44"
+   stepping = "1"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
+   extfeature_edx = "i64 syscall xd"
+   extfeature_ecx = "lahf_lm"
+   xlevel = "0x8000000A"
+   model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
+
+[cpudef]
+   name = "SandyBridge"
+   level = "0xd"
+   vendor = "GenuineIntel"
+   family = "6"
+   model = "42"
+   stepping = "1"
+   feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
+   extfeature_edx = "i64 rdtscp nx syscall "
+   extfeature_ecx = "lahf_lm"
+   xlevel = "0x8000000A"
+   model_id = "Intel Xeon E312xx (Sandy Bridge)"
+
+[cpudef]
+   name = "Opteron_G1"
+   level = "5"
+   vendor = "AuthenticAMD"
+   family = "15"
+   model = "6"
+   stepping = "1"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "sse3"
+   extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_ecx = " "
+   xlevel = "0x80000008"
+   model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
+
+[cpudef]
+   name = "Opteron_G2"
+   level = "5"
+   vendor = "AuthenticAMD"
+   family = "15"
+   model = "6"
+   stepping = "1"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "cx16 sse3"
+   extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_ecx = "svm lahf_lm"
+   xlevel = "0x80000008"
+   model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
+
+[cpudef]
+   name = "Opteron_G3"
+   level = "5"
+   vendor = "AuthenticAMD"
+   family = "15"
+   model = "6"
+   stepping = "1"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "popcnt cx16 monitor sse3"
+   extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
+   xlevel = "0x80000008"
+   model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
+
+[cpudef]
+   name = "Opteron_G4"
+   level = "0xd"
+   vendor = "AuthenticAMD"
+   family = "21"
+   model = "1"
+   stepping = "2"
+   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
+   feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
+   extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
+   extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm lahf_lm"
+   xlevel = "0x8000001A"
+   model_id = "AMD Opteron 62xx class CPU"
diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index cee0ea9..e69de29 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -1,128 +0,0 @@
-# x86 CPU MODELS
-
-[cpudef]
-   name = "Conroe"
-   level = "2"
-   vendor = "GenuineIntel"
-   family = "6"
-   model = "2"
-   stepping = "3"
-   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "ssse3 sse3"
-   extfeature_edx = "i64 xd syscall"
-   extfeature_ecx = "lahf_lm"
-   xlevel = "0x8000000A"
-   model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
-
-[cpudef]
-   name = "Penryn"
-   level = "2"
-   vendor = "GenuineIntel"
-   family = "6"
-   model = "2"
-   stepping = "3"
-   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "sse4.1 cx16 ssse3 sse3"
-   extfeature_edx = "i64 xd syscall"
-   extfeature_ecx = "lahf_lm"
-   xlevel = "0x8000000A"
-   model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
-
-[cpudef]
-   name = "Nehalem"
-   level = "2"
-   vendor = "GenuineIntel"
-   family = "6"
-   model = "2"
-   stepping = "3"
-   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
-   extfeature_edx = "i64 syscall xd"
-   extfeature_ecx = "lahf_lm"
-   xlevel = "0x8000000A"
-   model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
-
-[cpudef]
-   name = "Westmere"
-   level = "11"
-   vendor = "GenuineIntel"
-   family = "6"
-   model = "44"
-   stepping = "1"
-   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
-   extfeature_edx = "i64 syscall xd"
-   extfeature_ecx = "lahf_lm"
-   xlevel = "0x8000000A"
-   model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
-
-[cpudef]
-   name = "SandyBridge"
-   level = "0xd"
-   vendor = "GenuineIntel"
-   family = "6"
-   model = "42"
-   stepping = "1"
-   feature_edx = " sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "avx xsave aes tsc-deadline popcnt x2apic sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
-   extfeature_edx = "i64 rdtscp nx syscall "
-   extfeature_ecx = "lahf_lm"
-   xlevel = "0x8000000A"
-   model_id = "Intel Xeon E312xx (Sandy Bridge)"
-
-[cpudef]
-   name = "Opteron_G1"
-   level = "5"
-   vendor = "AuthenticAMD"
-   family = "15"
-   model = "6"
-   stepping = "1"
-   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "sse3"
-   extfeature_edx = "lm fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
-   extfeature_ecx = " "
-   xlevel = "0x80000008"
-   model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
-
-[cpudef]
-   name = "Opteron_G2"
-   level = "5"
-   vendor = "AuthenticAMD"
-   family = "15"
-   model = "6"
-   stepping = "1"
-   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "cx16 sse3"
-   extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
-   extfeature_ecx = "svm lahf_lm"
-   xlevel = "0x80000008"
-   model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
-
-[cpudef]
-   name = "Opteron_G3"
-   level = "5"
-   vendor = "AuthenticAMD"
-   family = "15"
-   model = "6"
-   stepping = "1"
-   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "popcnt cx16 monitor sse3"
-   extfeature_edx = "lm rdtscp fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
-   extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
-   xlevel = "0x80000008"
-   model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
-
-[cpudef]
-   name = "Opteron_G4"
-   level = "0xd"
-   vendor = "AuthenticAMD"
-   family = "21"
-   model = "1"
-   stepping = "2"
-   feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
-   feature_ecx = "avx xsave aes popcnt sse4.2 sse4.1 cx16 ssse3 pclmulqdq sse3"
-   extfeature_edx = "lm rdtscp pdpe1gb fxsr mmx nx pse36 pat cmov mca pge mtrr syscall apic cx8 mce pae msr tsc pse de fpu"
-   extfeature_ecx = " fma4 xop 3dnowprefetch misalignsse sse4a abm svm lahf_lm"
-   xlevel = "0x8000001A"
-   model_id = "AMD Opteron 62xx class CPU"
-
-- 
1.7.3.2