From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>
Subject: [Qemu-devel] [PATCH 03/15] tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
Date: Sun, 25 Mar 2012 15:27:45 -0700 [thread overview]
Message-ID: <1332714477-30079-4-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1332714477-30079-1-git-send-email-rth@twiddle.net>
Current code doesn't actually work in 32-bit mode at all. Since
no one really noticed, drop the complication of v7 and v8 cpus.
Eliminate the --sparc_cpu configure option and standardize macro
testing on TCG_TARGET_REG_BITS.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
configure | 41 ++++-------------------------------------
dyngen-exec.h | 4 +---
tcg/sparc/tcg-target.c | 16 ++++------------
tcg/sparc/tcg-target.h | 7 ++++---
4 files changed, 13 insertions(+), 55 deletions(-)
diff --git a/configure b/configure
index 80ca430..7741ba9 100755
--- a/configure
+++ b/configure
@@ -86,7 +86,6 @@ source_path=`dirname "$0"`
cpu=""
interp_prefix="/usr/gnemul/qemu-%M"
static="no"
-sparc_cpu=""
cross_prefix=""
audio_drv_list=""
audio_card_list="ac97 es1370 sb16 hda"
@@ -216,21 +215,6 @@ for opt do
;;
--disable-debug-info) debug_info="no"
;;
- --sparc_cpu=*)
- sparc_cpu="$optarg"
- case $sparc_cpu in
- v7|v8|v8plus|v8plusa)
- cpu="sparc"
- ;;
- v9)
- cpu="sparc64"
- ;;
- *)
- echo "undefined SPARC architecture. Exiting";
- exit 1
- ;;
- esac
- ;;
esac
done
# OS specific
@@ -284,8 +268,6 @@ elif check_define __i386__ ; then
elif check_define __x86_64__ ; then
cpu="x86_64"
elif check_define __sparc__ ; then
- # We can't check for 64 bit (when gcc is biarch) or V8PLUSA
- # They must be specified using --sparc_cpu
if check_define __arch64__ ; then
cpu="sparc64"
else
@@ -749,8 +731,6 @@ for opt do
;;
--enable-uname-release=*) uname_release="$optarg"
;;
- --sparc_cpu=*)
- ;;
--enable-werror) werror="yes"
;;
--disable-werror) werror="no"
@@ -830,32 +810,19 @@ for opt do
esac
done
-#
-# If cpu ~= sparc and sparc_cpu hasn't been defined, plug in the right
-# QEMU_CFLAGS/LDFLAGS (assume sparc_v8plus for 32-bit and sparc_v9 for 64-bit)
-#
host_guest_base="no"
case "$cpu" in
- sparc) case $sparc_cpu in
- v7|v8)
- QEMU_CFLAGS="-mcpu=${sparc_cpu} -D__sparc_${sparc_cpu}__ $QEMU_CFLAGS"
- ;;
- v8plus|v8plusa)
- QEMU_CFLAGS="-mcpu=ultrasparc -D__sparc_${sparc_cpu}__ $QEMU_CFLAGS"
- ;;
- *) # sparc_cpu not defined in the command line
- QEMU_CFLAGS="-mcpu=ultrasparc -D__sparc_v8plus__ $QEMU_CFLAGS"
- esac
+ sparc)
LDFLAGS="-m32 $LDFLAGS"
- QEMU_CFLAGS="-m32 -ffixed-g2 -ffixed-g3 $QEMU_CFLAGS"
+ QEMU_CFLAGS="-m32 -mcpu=ultrasparc $QEMU_CFLAGS"
+ QEMU_CFLAGS="-ffixed-g2 -ffixed-g3 $QEMU_CFLAGS"
if test "$solaris" = "no" ; then
QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
- helper_cflags="-ffixed-i0"
fi
;;
sparc64)
- QEMU_CFLAGS="-m64 -mcpu=ultrasparc -D__sparc_v9__ $QEMU_CFLAGS"
LDFLAGS="-m64 $LDFLAGS"
+ QEMU_CFLAGS="-m64 -mcpu=ultrasparc $QEMU_CFLAGS"
QEMU_CFLAGS="-ffixed-g5 -ffixed-g6 -ffixed-g7 $QEMU_CFLAGS"
if test "$solaris" != "no" ; then
QEMU_CFLAGS="-ffixed-g1 $QEMU_CFLAGS"
diff --git a/dyngen-exec.h b/dyngen-exec.h
index 083e20b..cfeef99 100644
--- a/dyngen-exec.h
+++ b/dyngen-exec.h
@@ -39,13 +39,11 @@
#elif defined(__sparc__)
#ifdef CONFIG_SOLARIS
#define AREG0 "g2"
-#else
-#ifdef __sparc_v9__
+#elif HOST_LONG_BITS == 64
#define AREG0 "g5"
#else
#define AREG0 "g6"
#endif
-#endif
#elif defined(__s390__)
#define AREG0 "r10"
#elif defined(__alpha__)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 358a70c..257d20a 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -627,18 +627,10 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
default:
tcg_out_cmp(s, c1, c2, c2const);
-#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
tcg_out_movi_imm13(s, ret, 0);
- tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
- | INSN_RS1(tcg_cond_to_bcond[cond])
- | MOVCC_ICC | INSN_IMM11(1));
-#else
- t = gen_new_label();
- tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
- tcg_out_movi_imm13(s, ret, 1);
- tcg_out_movi_imm13(s, ret, 0);
- tcg_out_label(s, t, s->code_ptr);
-#endif
+ tcg_out32(s, ARITH_MOVCC | INSN_RD(ret)
+ | INSN_RS1(tcg_cond_to_bcond[cond])
+ | MOVCC_ICC | INSN_IMM11(1));
return;
}
@@ -768,7 +760,7 @@ static const void * const qemu_st_helpers[4] = {
#endif
#endif
-#ifdef __arch64__
+#if TCG_TARGET_REG_BITS == 64
#define HOST_LD_OP LDX
#define HOST_ST_OP STX
#define HOST_SLL_OP SHIFT_SLLX
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index ee2274d..56742bf 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -67,7 +67,8 @@ typedef enum {
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_I6
-#ifdef __arch64__
+
+#if TCG_TARGET_REG_BITS == 64
// Reserve space for AREG0
#define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \
TCG_STATIC_CALL_ARGS_SIZE)
@@ -81,7 +82,7 @@ typedef enum {
#define TCG_TARGET_STACK_ALIGN 8
#endif
-#ifdef __arch64__
+#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_EXTEND_ARGS 1
#endif
@@ -128,7 +129,7 @@ typedef enum {
/* Note: must be synced with dyngen-exec.h */
#ifdef CONFIG_SOLARIS
#define TCG_AREG0 TCG_REG_G2
-#elif defined(__sparc_v9__)
+#elif HOST_LONG_BITS == 64
#define TCG_AREG0 TCG_REG_G5
#else
#define TCG_AREG0 TCG_REG_G6
--
1.7.7.6
next prev parent reply other threads:[~2012-03-25 22:28 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-25 22:27 [Qemu-devel] [PATCH 00/15] tcg-sparc improvments Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 01/15] tcg-sparc: Hack in qemu_ld/st64 for 32-bit Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 02/15] tcg-sparc: Fix ADDX opcode Richard Henderson
2012-03-25 22:27 ` Richard Henderson [this message]
2012-03-25 22:27 ` [Qemu-devel] [PATCH 04/15] tcg-sparc: Fix qemu_ld/st to handle 32-bit host Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 05/15] tcg-sparc: Simplify qemu_ld/st direct memory paths Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 06/15] tcg-sparc: Support GUEST_BASE Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 07/15] tcg-sparc: Steamline qemu_ld/st more Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 08/15] Avoid declaring the env variable at all if CONFIG_TCG_PASS_AREG0 Richard Henderson
2012-03-26 16:26 ` Blue Swirl
2012-03-26 16:31 ` Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 09/15] tcg-sparc: Do not use a global register for AREG0 Richard Henderson
2012-03-26 16:31 ` Blue Swirl
2012-03-26 16:52 ` Richard Henderson
2012-03-26 17:22 ` Blue Swirl
2012-03-25 22:27 ` [Qemu-devel] [PATCH 10/15] tcg-sparc: Change AREG0 in generated code to %i0 Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 11/15] tcg-sparc: Clean up cruft stemming from attempts to use global registers Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 12/15] tcg-sparc: Mask shift immediates to avoid illegal insns Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 13/15] tcg-sparc: Use defines for temporaries Richard Henderson
2012-03-26 16:38 ` Blue Swirl
2012-03-25 22:27 ` [Qemu-devel] [PATCH 14/15] tcg-sparc: Add %g/%o registers to alloc_order Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 15/15] tcg-sparc: Fix and enable direct TB chaining Richard Henderson
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