From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>
Subject: [Qemu-devel] [PATCH 06/15] tcg-sparc: Support GUEST_BASE.
Date: Sun, 25 Mar 2012 15:27:48 -0700 [thread overview]
Message-ID: <1332714477-30079-7-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1332714477-30079-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
configure | 2 ++
tcg/sparc/tcg-target.c | 40 +++++++++++++++++++++++++++++-----------
tcg/sparc/tcg-target.h | 2 ++
3 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/configure b/configure
index 7741ba9..a79a090 100755
--- a/configure
+++ b/configure
@@ -819,6 +819,7 @@ case "$cpu" in
if test "$solaris" = "no" ; then
QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
fi
+ host_guest_base="yes"
;;
sparc64)
LDFLAGS="-m64 $LDFLAGS"
@@ -827,6 +828,7 @@ case "$cpu" in
if test "$solaris" != "no" ; then
QEMU_CFLAGS="-ffixed-g1 $QEMU_CFLAGS"
fi
+ host_guest_base="yes"
;;
s390)
QEMU_CFLAGS="-m31 -march=z990 $QEMU_CFLAGS"
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 1b27626..9891648 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -59,6 +59,12 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
};
#endif
+#ifdef CONFIG_USE_GUEST_BASE
+# define TCG_GUEST_BASE_REG TCG_REG_I3
+#else
+# define TCG_GUEST_BASE_REG TCG_REG_G0
+#endif
+
#ifdef CONFIG_TCG_PASS_AREG0
#define ARG_OFFSET 1
#else
@@ -689,6 +695,14 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME +
CPU_TEMP_BUF_NLONGS * (int)sizeof(long))));
+
+#ifdef CONFIG_USE_GUEST_BASE
+ if (GUEST_BASE != 0) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) |
INSN_RS2(TCG_REG_G0));
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0);
@@ -819,8 +833,8 @@ static int tcg_out_tlb_load(TCGContext *s, int addrlo_idx, int mem_index,
}
#endif /* CONFIG_SOFTMMU */
-static void tcg_out_qemu_ld_direct(TCGContext *s, int addr, int datalo,
- int datahi, int sizeop)
+static void tcg_out_qemu_ld_direct(TCGContext *s, int addr, int addend,
+ int datalo, int datahi, int sizeop)
{
#ifdef TARGET_WORDS_BIGENDIAN
static const int ld_opc[8] = {
@@ -835,14 +849,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int addr, int datalo,
if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
/* Load all 64-bits into an O/G register. */
int reg64 = (datalo < 16 ? datalo : TCG_REG_O0);
- tcg_out_ldst_rr(s, reg64, addr, TCG_REG_G0, ld_opc[sizeop]);
+ tcg_out_ldst_rr(s, reg64, addr, addend, ld_opc[sizeop]);
/* Move the two 32-bit pieces into the destination registers. */
tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX);
if (reg64 != datalo) {
tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64);
}
} else {
- tcg_out_ldst_rr(s, datalo, addr, TCG_REG_G0, ld_opc[sizeop]);
+ tcg_out_ldst_rr(s, datalo, addr, addend, ld_opc[sizeop]);
}
}
@@ -869,7 +883,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
label_ptr, offsetof(CPUTLBEntry, addr_read));
/* TLB Hit. */
- tcg_out_qemu_ld_direct(s, addr_reg, datalo, datahi, opc);
+ tcg_out_qemu_ld_direct(s, addr_reg, TCG_REG_G0, datalo, datahi, opc);
/* b,pt,n label1 */
label_ptr[1] = (uint32_t *)s->code_ptr;
@@ -948,12 +962,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_out_arithi(s, TCG_REG_I5, addr_reg, 0, SHIFT_SRL);
addr_reg = TCG_REG_I5;
}
- tcg_out_qemu_ld_direct(s, addr_reg, datalo, datahi, opc);
+ tcg_out_qemu_ld_direct(s, addr_reg,
+ (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
+ datalo, datahi, opc);
#endif /* CONFIG_SOFTMMU */
}
-static void tcg_out_qemu_st_direct(TCGContext *s, int addr, int datalo,
- int datahi, int sizeop)
+static void tcg_out_qemu_st_direct(TCGContext *s, int addr, int addend,
+ int datalo, int datahi, int sizeop)
{
#ifdef TARGET_WORDS_BIGENDIAN
static const int st_opc[4] = { STB, STH, STW, STX };
@@ -967,7 +983,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int addr, int datalo,
tcg_out_arith(s, TCG_REG_O0, TCG_REG_O0, TCG_REG_O2, ARITH_OR);
datalo = TCG_REG_O0;
}
- tcg_out_ldst_rr(s, datalo, addr, TCG_REG_G0, st_opc[sizeop]);
+ tcg_out_ldst_rr(s, datalo, addr, addend, st_opc[sizeop]);
}
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
@@ -992,7 +1008,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
label_ptr, offsetof(CPUTLBEntry, addr_write));
/* TLB Hit. */
- tcg_out_qemu_st_direct(s, addr_reg, datalo, datahi, opc);
+ tcg_out_qemu_st_direct(s, addr_reg, TCG_REG_G0, datalo, datahi, opc);
/* b,pt,n label1 */
label_ptr[1] = (uint32_t *)s->code_ptr;
@@ -1045,7 +1061,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_out_arithi(s, TCG_REG_I5, addr_reg, 0, SHIFT_SRL);
addr_reg = TCG_REG_I5;
}
- tcg_out_qemu_st_direct(s, addr_reg, datalo, datahi, opc);
+ tcg_out_qemu_st_direct(s, addr_reg,
+ (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
+ datalo, datahi, opc);
#endif /* CONFIG_SOFTMMU */
}
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 56742bf..e69dfc8 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -126,6 +126,8 @@ typedef enum {
#define TCG_TARGET_HAS_deposit_i64 0
#endif
+#define TCG_TARGET_HAS_GUEST_BASE
+
/* Note: must be synced with dyngen-exec.h */
#ifdef CONFIG_SOLARIS
#define TCG_AREG0 TCG_REG_G2
--
1.7.7.6
next prev parent reply other threads:[~2012-03-25 22:28 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-25 22:27 [Qemu-devel] [PATCH 00/15] tcg-sparc improvments Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 01/15] tcg-sparc: Hack in qemu_ld/st64 for 32-bit Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 02/15] tcg-sparc: Fix ADDX opcode Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 03/15] tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 04/15] tcg-sparc: Fix qemu_ld/st to handle 32-bit host Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 05/15] tcg-sparc: Simplify qemu_ld/st direct memory paths Richard Henderson
2012-03-25 22:27 ` Richard Henderson [this message]
2012-03-25 22:27 ` [Qemu-devel] [PATCH 07/15] tcg-sparc: Steamline qemu_ld/st more Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 08/15] Avoid declaring the env variable at all if CONFIG_TCG_PASS_AREG0 Richard Henderson
2012-03-26 16:26 ` Blue Swirl
2012-03-26 16:31 ` Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 09/15] tcg-sparc: Do not use a global register for AREG0 Richard Henderson
2012-03-26 16:31 ` Blue Swirl
2012-03-26 16:52 ` Richard Henderson
2012-03-26 17:22 ` Blue Swirl
2012-03-25 22:27 ` [Qemu-devel] [PATCH 10/15] tcg-sparc: Change AREG0 in generated code to %i0 Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 11/15] tcg-sparc: Clean up cruft stemming from attempts to use global registers Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 12/15] tcg-sparc: Mask shift immediates to avoid illegal insns Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 13/15] tcg-sparc: Use defines for temporaries Richard Henderson
2012-03-26 16:38 ` Blue Swirl
2012-03-25 22:27 ` [Qemu-devel] [PATCH 14/15] tcg-sparc: Add %g/%o registers to alloc_order Richard Henderson
2012-03-25 22:27 ` [Qemu-devel] [PATCH 15/15] tcg-sparc: Fix and enable direct TB chaining Richard Henderson
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