From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37676) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCdwM-0001vu-N1 for qemu-devel@nongnu.org; Tue, 27 Mar 2012 17:28:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SCdwJ-0002ia-2I for qemu-devel@nongnu.org; Tue, 27 Mar 2012 17:28:30 -0400 Received: from e39.co.us.ibm.com ([32.97.110.160]:43981) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCdwI-0002go-Qf for qemu-devel@nongnu.org; Tue, 27 Mar 2012 17:28:26 -0400 Received: from /spool/local by e39.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 27 Mar 2012 15:28:25 -0600 Received: from d03relay05.boulder.ibm.com (d03relay05.boulder.ibm.com [9.17.195.107]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 0570419D8050 for ; Tue, 27 Mar 2012 15:27:49 -0600 (MDT) Received: from d03av03.boulder.ibm.com (d03av03.boulder.ibm.com [9.17.195.169]) by d03relay05.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q2RLRSjj223374 for ; Tue, 27 Mar 2012 15:27:32 -0600 Received: from d03av03.boulder.ibm.com (loopback [127.0.0.1]) by d03av03.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q2RLRPnJ027067 for ; Tue, 27 Mar 2012 15:27:27 -0600 From: Stefan Berger Date: Tue, 27 Mar 2012 16:24:35 -0400 Message-Id: <1332879879-29460-4-git-send-email-stefanb@linux.vnet.ibm.com> In-Reply-To: <1332879879-29460-1-git-send-email-stefanb@linux.vnet.ibm.com> References: <1332879879-29460-1-git-send-email-stefanb@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH V15 3/7] Add a debug register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: stefanb@linux.vnet.ibm.com, qemu-devel@nongnu.org, anthony@codemonkey.ws Cc: andreas.niederl@iaik.tugraz.at, mst@redhat.com This patch uses the possibility to add a vendor-specific register and adds a debug register useful for dumping the TIS's internal state. This register is only active in a debug build (#define DEBUG_TIS). Signed-off-by: Stefan Berger --- hw/tpm_tis.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) diff --git a/hw/tpm_tis.c b/hw/tpm_tis.c index c9bb899..0abd8f3 100644 --- a/hw/tpm_tis.c +++ b/hw/tpm_tis.c @@ -55,6 +55,9 @@ #define TPM_TIS_REG_DID_VID 0xf00 #define TPM_TIS_REG_RID 0xf04 +/* vendor-specific registers */ +#define TPM_TIS_REG_DEBUG 0xf90 + #define TPM_TIS_STS_VALID (1 << 7) #define TPM_TIS_STS_COMMAND_READY (1 << 6) #define TPM_TIS_STS_TPM_GO (1 << 5) @@ -100,6 +103,11 @@ #define TPM_TIS_NO_DATA_BYTE 0xff +/* local prototypes */ + +static uint64_t tpm_tis_mmio_read(void *opaque, target_phys_addr_t addr, + unsigned size); + /* utility functions */ static uint8_t tpm_tis_locality_from_addr(target_phys_addr_t addr) @@ -334,6 +342,63 @@ static uint32_t tpm_tis_data_read(TPMState *s, uint8_t locty) return ret; } +#ifdef DEBUG_TIS +static void tpm_tis_dump_state(void *opaque, target_phys_addr_t addr) +{ + static const unsigned regs[] = { + TPM_TIS_REG_ACCESS, + TPM_TIS_REG_INT_ENABLE, + TPM_TIS_REG_INT_VECTOR, + TPM_TIS_REG_INT_STATUS, + TPM_TIS_REG_INTF_CAPABILITY, + TPM_TIS_REG_STS, + TPM_TIS_REG_DID_VID, + TPM_TIS_REG_RID, + 0xfff}; + int idx; + uint8_t locty = tpm_tis_locality_from_addr(addr); + target_phys_addr_t base = addr & ~0xfff; + TPMState *s = opaque; + TPMTISState *tis = &s->s.tis; + + dprintf("tpm_tis: active locality : %d\n" + "tpm_tis: state of locality %d : %d\n" + "tpm_tis: register dump:\n", + tis->active_locty, + locty, tis->loc[locty].status); + + for (idx = 0; regs[idx] != 0xfff; idx++) { + dprintf("tpm_tis: 0x%04x : 0x%08x\n", regs[idx], + (uint32_t)tpm_tis_mmio_read(opaque, base + regs[idx], 4)); + } + + dprintf("tpm_tis: read offset : %d\n" + "tpm_tis: result buffer : ", + tis->loc[locty].r_offset); + for (idx = 0; + idx < tpm_tis_get_size_from_buffer(&tis->loc[locty].r_buffer); + idx++) { + dprintf("%c%02x%s", + tis->loc[locty].r_offset == idx ? '>' : ' ', + tis->loc[locty].r_buffer.buffer[idx], + ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); + } + dprintf("\n" + "tpm_tis: write offset : %d\n" + "tpm_tis: request buffer: ", + tis->loc[locty].w_offset); + for (idx = 0; + idx < tpm_tis_get_size_from_buffer(&tis->loc[locty].w_buffer); + idx++) { + dprintf("%c%02x%s", + tis->loc[locty].w_offset == idx ? '>' : ' ', + tis->loc[locty].w_buffer.buffer[idx], + ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); + } + dprintf("\n"); +} +#endif + /* * Read a register of the TIS interface * See specs pages 33-63 for description of the registers @@ -403,6 +468,11 @@ static uint64_t tpm_tis_mmio_read(void *opaque, target_phys_addr_t addr, case TPM_TIS_REG_RID: val = TPM_TIS_TPM_RID; break; +#ifdef DEBUG_TIS + case TPM_TIS_REG_DEBUG: + tpm_tis_dump_state(opaque, addr); + break; +#endif } if (shift) { -- 1.7.4.4