From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52871) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDIw6-0002pK-Vy for qemu-devel@nongnu.org; Thu, 29 Mar 2012 13:15:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDIvw-0000Tp-QS for qemu-devel@nongnu.org; Thu, 29 Mar 2012 13:14:58 -0400 Received: from cantor2.suse.de ([195.135.220.15]:52011 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDIvw-0000T7-HD for qemu-devel@nongnu.org; Thu, 29 Mar 2012 13:14:48 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 29 Mar 2012 19:14:37 +0200 Message-Id: <1333041282-3254-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 0/5] QOM'ify UniCore32 CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Guan Xue-tao , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Anthony Liguori Hello Xuetao, This updated series converts the UniCore32 CPU to QOM. In addition to addressing review comments from v1, a new approach for CPU-dependent values has been adopted: We should keep setting of features imperative and can avoid adding new class fields as storage for default values by moving the existing imperative code into new initfn functions. Patch 1 adds a "UniCore32 CPU guest core (TCG)" section to MAINTAINERS, so that the target-unicore32 author gets notified of patches against his = code. Patch 2, based on feedback from Guan Xuetao, changes the license of most target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a qemu_malloc() -> g_malloc() substitution that he can't relicense at this = time, so leave that as GPLv2 and declare my following patches explicitly as GPL= v2+. Patch 3 adds a notice to license any following contributions under GPLv2+= already. Patch 4 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h head= er can be GPLv2+, but into cpu.c we're moving helper.c code so make it GPLv2= for now. Patch 5 cleans up uc32_cpu_init() function by moving initializations into= initfn. Could you test this please and, if happy, provide your Acked-by for patch= es 1 and 3-5? Available from: git://github.com/afaerber/qemu-cpu.git qom-cpu-unicore32.v2 https://github.com/afaerber/qemu-cpu/commits/qom-cpu-unicore32.v2 Regards, Andreas Cc: Guan Xue-tao Cc: Anthony Liguori Cc: Peter Maydell v1 -> v2: * Change license notice to match the previous one more closely. * Adopt that license notice for new cpu-qom.h as well. * Add notices to helper.c and cpu.c to license future contributions under= GPLv2+. * Adopt Peter's approach of using per-CPU initfn functions for default va= lues. * Squash init code movement together (no new UniCore32CPUClass members ne= eded). * Various naming updates (e.g., ..._type_info). Changes from former repo.or.cz qom-cpu[-wip] branch: * Drop duplicate .instance_init. Andreas F=C3=A4rber (5): MAINTAINERS: Add entry for UniCore32 target-unicore32: Relicense to GPLv2+ target-unicore32: License future contributions under GPLv2+ target-unicore32: QOM'ify CPU target-unicore32: Move CPU-dependent init into initfn MAINTAINERS | 5 ++ Makefile.target | 1 + target-unicore32/cpu-qom.h | 59 ++++++++++++++++++++++++ target-unicore32/cpu.c | 104 ++++++++++++++++++++++++++++++++++++= ++++++ target-unicore32/cpu.h | 4 +- target-unicore32/helper.c | 65 +++----------------------- target-unicore32/helper.h | 3 +- target-unicore32/op_helper.c | 3 +- target-unicore32/translate.c | 3 +- 9 files changed, 186 insertions(+), 61 deletions(-) create mode 100644 target-unicore32/cpu-qom.h create mode 100644 target-unicore32/cpu.c --=20 1.7.7