[Qemu-devel] [PULL 0/3] target-arm queue

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Pending target-arm patches; not very many, but seems better to
commit them now, since there might be further trustzone related
patches that would have to sit on top of these. Please pull.

The following changes since commit c47f3223658119219bbe0b8d09da733d1c06e76f:

  Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into staging (2012-01-04 10:06:25 -0600)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Mark Langsdorf (1):
      arm: add dummy A9-specific cp15 registers

Peter Maydell (2):
      target-arm: Don't use cpu_single_env in bank_number()
      target-arm: Ignore attempts to set invalid modes in CPSR

 target-arm/cpu.h     |    6 +++-
 target-arm/helper.c  |   90 ++++++++++++++++++++++++++++++++++++++++++++++----
 target-arm/machine.c |    6 +++
 3 files changed, 94 insertions(+), 8 deletions(-)

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Aurelien Jarno]

On Thu, Jan 05, 2012 at 04:44:31PM +0000, Peter Maydell wrote:
> Pending target-arm patches; not very many, but seems better to
> commit them now, since there might be further trustzone related
> patches that would have to sit on top of these. Please pull.
> 
> The following changes since commit c47f3223658119219bbe0b8d09da733d1c06e76f:
> 
>   Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into staging (2012-01-04 10:06:25 -0600)
> 
> are available in the git repository at:
> 
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
> 
> Mark Langsdorf (1):
>       arm: add dummy A9-specific cp15 registers
> 
> Peter Maydell (2):
>       target-arm: Don't use cpu_single_env in bank_number()
>       target-arm: Ignore attempts to set invalid modes in CPSR
> 
>  target-arm/cpu.h     |    6 +++-
>  target-arm/helper.c  |   90 ++++++++++++++++++++++++++++++++++++++++++++++----
>  target-arm/machine.c |    6 +++
>  3 files changed, 94 insertions(+), 8 deletions(-)
> 
> 

Thanks, pulled.

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Hi; this is a pullreq for my target-arm queue. Just three fairly
minor bug fixes this time. Please pull.

Thanks
-- PMM

The following changes since commit ae7d54d489540b49b7c13a7df7ddc220588a2ced:

  target-lm32/microblaze: Drop second CPU{LM32, MB}State typedef (2012-03-14 19:48:37 -0500)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Peter Maydell (3):
      target-arm: Fix typo in ARM946 cp15 c5 handling
      target-arm: Clear IT bits when taking exceptions in v7M
      target-arm: Decode SETEND correctly in Thumb

 target-arm/helper.c    |    5 ++-
 target-arm/translate.c |   63 ++++++++++++++++++++++++++++++-----------------
 2 files changed, 43 insertions(+), 25 deletions(-)

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Blue Swirl]

On Fri, Mar 16, 2012 at 18:21, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is a pullreq for my target-arm queue. Just three fairly
> minor bug fixes this time. Please pull.

Thanks, pulled.

> Thanks
> -- PMM
>
> The following changes since commit ae7d54d489540b49b7c13a7df7ddc220588a2ced:
>
>  target-lm32/microblaze: Drop second CPU{LM32, MB}State typedef (2012-03-14 19:48:37 -0500)
>
> are available in the git repository at:
>  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> Peter Maydell (3):
>      target-arm: Fix typo in ARM946 cp15 c5 handling
>      target-arm: Clear IT bits when taking exceptions in v7M
>      target-arm: Decode SETEND correctly in Thumb
>
>  target-arm/helper.c    |    5 ++-
>  target-arm/translate.c |   63 ++++++++++++++++++++++++++++++-----------------
>  2 files changed, 43 insertions(+), 25 deletions(-)

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Hi; this is a pullreq for my target-arm queue; please pull.

The following changes since commit f638f0d3ae214d995cdd94578195700cda24597b:

  qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs (2012-03-29 11:10:08 +0400)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Andreas Färber (2):
      target-arm: Drop cpu_arm_close()
      target-arm: Minimalistic CPU QOM'ification

Andrew Towers (1):
      ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.

 Makefile.target        |    1 +
 target-arm/cpu-qom.h   |   71 ++++++++++++++++++++++++++++++++++++++++++++++++
 target-arm/cpu.c       |   60 ++++++++++++++++++++++++++++++++++++++++
 target-arm/cpu.h       |    3 +-
 target-arm/helper.c    |   14 +++++----
 target-arm/translate.c |    2 +-
 6 files changed, 143 insertions(+), 8 deletions(-)
 create mode 100644 target-arm/cpu-qom.h
 create mode 100644 target-arm/cpu.c

[Qemu-devel] [PATCH 1/3] target-arm: Drop cpu_arm_close()

[Peter Maydell]

From: Andreas Färber <afaerber@suse.de>

It's unused, so no need to QOM'ify it later.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.h    |    1 -
 target-arm/helper.c |    5 -----
 2 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 26c114b..69ef142 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -238,7 +238,6 @@ typedef struct CPUARMState {
 CPUARMState *cpu_arm_init(const char *cpu_model);
 void arm_translate_init(void);
 int cpu_arm_exec(CPUARMState *s);
-void cpu_arm_close(CPUARMState *s);
 void do_interrupt(CPUARMState *);
 void switch_mode(CPUARMState *, int);
 uint32_t do_arm_semihosting(CPUARMState *env);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1314f23..1ce8105 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -493,11 +493,6 @@ static uint32_t cpu_arm_find_by_name(const char *name)
     return id;
 }
 
-void cpu_arm_close(CPUARMState *env)
-{
-    g_free(env);
-}
-
 static int bad_mode_switch(CPUARMState *env, int mode)
 {
     /* Return true if it is not valid for us to switch to
-- 
1.7.1

[Qemu-devel] [PATCH 2/3] target-arm: Minimalistic CPU QOM'ification

[Peter Maydell]

From: Andreas Färber <afaerber@suse.de>

Introduce only one non-abstract type TYPE_ARM_CPU and do not touch
cp15 registers to not interfere with Peter's ongoing remodelling.
Embed CPUARMState as first (additional) field of ARMCPU.

Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 Makefile.target      |    1 +
 target-arm/cpu-qom.h |   71 ++++++++++++++++++++++++++++++++++++++++++++++++++
 target-arm/cpu.c     |   60 ++++++++++++++++++++++++++++++++++++++++++
 target-arm/cpu.h     |    1 +
 target-arm/helper.c  |    8 +++++-
 5 files changed, 140 insertions(+), 1 deletions(-)
 create mode 100644 target-arm/cpu-qom.h
 create mode 100644 target-arm/cpu.c

diff --git a/Makefile.target b/Makefile.target
index 44b2e83..6e8b997 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -92,6 +92,7 @@ endif
 libobj-$(TARGET_SPARC64) += vis_helper.o
 libobj-$(CONFIG_NEED_MMU) += mmu.o
 libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
+libobj-$(TARGET_ARM) += cpu.o
 ifeq ($(TARGET_BASE_ARCH), sparc)
 libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
 libobj-y += cpu_init.o
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
new file mode 100644
index 0000000..42d2a6b
--- /dev/null
+++ b/target-arm/cpu-qom.h
@@ -0,0 +1,71 @@
+/*
+ * QEMU ARM CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+#ifndef QEMU_ARM_CPU_QOM_H
+#define QEMU_ARM_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_ARM_CPU "arm-cpu"
+
+#define ARM_CPU_CLASS(klass) \
+    OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
+#define ARM_CPU(obj) \
+    OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
+#define ARM_CPU_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
+
+/**
+ * ARMCPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An ARM CPU model.
+ */
+typedef struct ARMCPUClass {
+    /*< private >*/
+    CPUClass parent_class;
+    /*< public >*/
+
+    void (*parent_reset)(CPUState *cpu);
+} ARMCPUClass;
+
+/**
+ * ARMCPU:
+ * @env: #CPUARMState
+ *
+ * An ARM CPU core.
+ */
+typedef struct ARMCPU {
+    /*< private >*/
+    CPUState parent_obj;
+    /*< public >*/
+
+    CPUARMState env;
+} ARMCPU;
+
+static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
+{
+    return ARM_CPU(container_of(env, ARMCPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
+
+
+#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
new file mode 100644
index 0000000..c3ed45b
--- /dev/null
+++ b/target-arm/cpu.c
@@ -0,0 +1,60 @@
+/*
+ * QEMU ARM CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+/* CPUClass::reset() */
+static void arm_cpu_reset(CPUState *s)
+{
+    ARMCPU *cpu = ARM_CPU(s);
+    ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
+
+    acc->parent_reset(s);
+
+    /* TODO Inline the current contents of cpu_state_reset(),
+            once cpu_reset_model_id() is eliminated. */
+    cpu_state_reset(&cpu->env);
+}
+
+static void arm_cpu_class_init(ObjectClass *oc, void *data)
+{
+    ARMCPUClass *acc = ARM_CPU_CLASS(oc);
+    CPUClass *cc = CPU_CLASS(acc);
+
+    acc->parent_reset = cc->reset;
+    cc->reset = arm_cpu_reset;
+}
+
+static const TypeInfo arm_cpu_type_info = {
+    .name = TYPE_ARM_CPU,
+    .parent = TYPE_CPU,
+    .instance_size = sizeof(ARMCPU),
+    .abstract = false,
+    .class_size = sizeof(ARMCPUClass),
+    .class_init = arm_cpu_class_init,
+};
+
+static void arm_cpu_register_types(void)
+{
+    type_register_static(&arm_cpu_type_info);
+}
+
+type_init(arm_cpu_register_types)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 69ef142..a68df61 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -475,6 +475,7 @@ static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
 #endif
 
 #include "cpu-all.h"
+#include "cpu-qom.h"
 
 /* Bit usage in the TB flags field: */
 #define ARM_TBFLAG_THUMB_SHIFT      0
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1ce8105..dd8e306 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -278,6 +278,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
     }
 }
 
+/* TODO Move contents into arm_cpu_reset() in cpu.c,
+ *      once cpu_reset_model_id() is eliminated,
+ *      and then forward to cpu_reset() here.
+ */
 void cpu_state_reset(CPUARMState *env)
 {
     uint32_t id;
@@ -400,6 +404,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 
 CPUARMState *cpu_arm_init(const char *cpu_model)
 {
+    ARMCPU *cpu;
     CPUARMState *env;
     uint32_t id;
     static int inited = 0;
@@ -407,7 +412,8 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
     id = cpu_arm_find_by_name(cpu_model);
     if (id == 0)
         return NULL;
-    env = g_malloc0(sizeof(CPUARMState));
+    cpu = ARM_CPU(object_new(TYPE_ARM_CPU));
+    env = &cpu->env;
     cpu_exec_init(env);
     if (tcg_enabled() && !inited) {
         inited = 1;
-- 
1.7.1

[Qemu-devel] [PATCH 3/3] ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.

[Peter Maydell]

From: Andrew Towers <atowers@gmail.com>

This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registers
with a test for a new feature flag ARM_FEATURE_MVFR, and sets this feature
for all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu
does not support ARM1156 at this time.)

MVFR0 and MVFR1 were introduced in ARM1136JF-S r1p0 (ARMv6K, VFPv2) and are
present in ARM1156T2F-S (non-v6K), ARM1176JZF-S, ARM11MPCore and newer cores.
Reference: ARM DDI 0211H, 0290G, 0301H, 0360E.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Ffbefjag.html

Without this change, the linux kernel will not boot with VFP support enabled
under ARM1176 system emulation, due to the unconditional use of MVFR1 at the
end of vfp_init() in arch/arm/vfp/vfpmodule.c:

  VFP support v0.3: implemetor 41 architecture 1 part 20 variant b rev 5
  Internal error: Oops - undefined instruction: 0 [#1]

Signed-off-by: Andrew Towers <atowers@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.h       |    1 +
 target-arm/helper.c    |    1 +
 target-arm/translate.c |    2 +-
 3 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a68df61..e176c5f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -382,6 +382,7 @@ enum arm_features {
     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
     ARM_FEATURE_GENERIC_TIMER,
+    ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 };
 
 static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index dd8e306..d974b57 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -254,6 +254,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
     }
     if (arm_feature(env, ARM_FEATURE_V6K)) {
         set_feature(env, ARM_FEATURE_V6);
+        set_feature(env, ARM_FEATURE_MVFR);
     }
     if (arm_feature(env, ARM_FEATURE_V6)) {
         set_feature(env, ARM_FEATURE_V5);
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 81725d1..46d1d3e 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2906,7 +2906,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
                         case ARM_VFP_MVFR0:
                         case ARM_VFP_MVFR1:
                             if (IS_USER(s)
-                                || !arm_feature(env, ARM_FEATURE_VFP3))
+                                || !arm_feature(env, ARM_FEATURE_MVFR))
                                 return 1;
                             tmp = load_cpu_field(vfp.xregs[rn]);
                             break;
-- 
1.7.1

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Blue Swirl]

On Fri, Mar 30, 2012 at 10:26, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is a pullreq for my target-arm queue; please pull.

Thanks, pulled.

> The following changes since commit f638f0d3ae214d995cdd94578195700cda24597b:
>
>  qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs (2012-03-29 11:10:08 +0400)
>
> are available in the git repository at:
>  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> Andreas Färber (2):
>      target-arm: Drop cpu_arm_close()
>      target-arm: Minimalistic CPU QOM'ification
>
> Andrew Towers (1):
>      ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.
>
>  Makefile.target        |    1 +
>  target-arm/cpu-qom.h   |   71 ++++++++++++++++++++++++++++++++++++++++++++++++
>  target-arm/cpu.c       |   60 ++++++++++++++++++++++++++++++++++++++++
>  target-arm/cpu.h       |    3 +-
>  target-arm/helper.c    |   14 +++++----
>  target-arm/translate.c |    2 +-
>  6 files changed, 143 insertions(+), 8 deletions(-)
>  create mode 100644 target-arm/cpu-qom.h
>  create mode 100644 target-arm/cpu.c

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Just three fairly small bugfixes...

-- PMM


The following changes since commit 8f280309030331a912fd8924c129d8bd59e1bdc7:

  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2015-11-18 17:07:24 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151119

for you to fetch changes up to ce8a1b5449cd8c4c2831abb581d3208c3a3745a0:

  target-arm: Update condexec before arch BP check in AA32 translation (2015-11-19 12:51:08 +0000)

----------------------------------------------------------------
target-arm queue:
 * add missing condexec updates when emulating architectural breakpoints
   and coprocessor access checks in Thumb translation (could in theory
   cause problems when these happened inside a Thumb IT block and an
   exception was taken)
 * arm_gic: correctly restore nested IRQ priority

----------------------------------------------------------------
François Baldassari (1):
      hw/arm_gic: Correctly restore nested irq priority

Sergey Fedorov (2):
      target-arm: Update condexec before CP access check in AA32 translation
      target-arm: Update condexec before arch BP check in AA32 translation

 hw/intc/arm_gic.c      | 4 ++--
 target-arm/translate.c | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

On 19 November 2015 at 13:31, Peter Maydell <peter.maydell@linaro.org> wrote:
> Just three fairly small bugfixes...
>
> -- PMM
>
>
> The following changes since commit 8f280309030331a912fd8924c129d8bd59e1bdc7:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2015-11-18 17:07:24 +0000)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151119
>
> for you to fetch changes up to ce8a1b5449cd8c4c2831abb581d3208c3a3745a0:
>
>   target-arm: Update condexec before arch BP check in AA32 translation (2015-11-19 12:51:08 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * add missing condexec updates when emulating architectural breakpoints
>    and coprocessor access checks in Thumb translation (could in theory
>    cause problems when these happened inside a Thumb IT block and an
>    exception was taken)
>  * arm_gic: correctly restore nested IRQ priority
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Last arm patches for rc3...

thanks
-- PMM

The following changes since commit 72138f9bf5d8c316043b0d2cc7a674f70930cf95:

  Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2018-11-26 11:46:04 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181126

for you to fetch changes up to 58102ce7fbb2362aa53984aabcf684d164da2d9d:

  net: cadence_gem: Remove incorrect assert() (2018-11-26 13:41:42 +0000)

----------------------------------------------------------------
target-arm queue:
 * some updates to MAINTAINERS file entries
 * cadence_gem: Remove an incorrect assert()

----------------------------------------------------------------
Edgar E. Iglesias (1):
      net: cadence_gem: Remove incorrect assert()

Eric Auger (1):
      MAINTAINERS: Add an ARM SMMU section

Thomas Huth (1):
      MAINTAINERS: Assign some more files in the hw/arm/ directory

 hw/net/cadence_gem.c |  1 -
 MAINTAINERS          | 23 +++++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

On Mon, 26 Nov 2018 at 14:00, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Last arm patches for rc3...
>
> thanks
> -- PMM
>
> The following changes since commit 72138f9bf5d8c316043b0d2cc7a674f70930cf95:
>
>   Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2018-11-26 11:46:04 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181126
>
> for you to fetch changes up to 58102ce7fbb2362aa53984aabcf684d164da2d9d:
>
>   net: cadence_gem: Remove incorrect assert() (2018-11-26 13:41:42 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * some updates to MAINTAINERS file entries
>  * cadence_gem: Remove an incorrect assert()
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM