[Qemu-devel] [PATCH 10/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset

[Peter Maydell <peter.maydell@linaro.org>]

Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset;
since these registers are only accessible on CPUs with the
OMAPCP feature set there's no need to guard this reset with
either a CPUID or feature bit check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6c21f74..a94f09f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -48,8 +48,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         break;
     case ARM_CPUID_TI915T:
     case ARM_CPUID_TI925T:
-        env->cp15.c15_i_max = 0x000;
-        env->cp15.c15_i_min = 0xff0;
         break;
     case ARM_CPUID_PXA250:
     case ARM_CPUID_PXA255:
@@ -115,6 +113,7 @@ void cpu_state_reset(CPUARMState *env)
     env->cp15.c0_c2[3] = cpu->id_isar3;
     env->cp15.c0_c2[4] = cpu->id_isar4;
     env->cp15.c0_c2[5] = cpu->id_isar5;
+    env->cp15.c15_i_min = 0xff0;
 
     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
-- 
1.7.1