From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33075) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDbJK-0001im-8I for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:52:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDbJD-0000Es-In for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:52:09 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:41204) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDbJD-0000Bv-3i for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:52:03 -0400 From: Peter Maydell Date: Fri, 30 Mar 2012 13:51:40 +0100 Message-Id: <1333111910-3641-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1333111910-3641-1-git-send-email-peter.maydell@linaro.org> References: <1333111910-3641-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 04/14] target-arm: Move MVFR* setup to per cpu init fns List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paul Brook , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= Move the MVFR* VFP feature register values to ARMCPU, so they are set up by the implementation-specific instance init functions rather than in cpu_reset_model_id(). Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 14 ++++++++++++++ target-arm/helper.c | 14 ++------------ 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index a842917..e63ff76 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -64,6 +64,8 @@ typedef struct ARMCPU { */ uint32_t midr; uint32_t reset_fpsid; + uint32_t mvfr0; + uint32_t mvfr1; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 2b881ac..444ba77 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -134,6 +134,8 @@ static void arm1136_r2_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM1136_R2; cpu->reset_fpsid = 0x410120b4; + cpu->mvfr0 = 0x11111111; + cpu->mvfr1 = 0x00000000; arm_cpu_postconfig_init(cpu); } @@ -145,6 +147,8 @@ static void arm1136_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->midr = ARM_CPUID_ARM1136; cpu->reset_fpsid = 0x410120b4; + cpu->mvfr0 = 0x11111111; + cpu->mvfr1 = 0x00000000; arm_cpu_postconfig_init(cpu); } @@ -156,6 +160,8 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VAPA); cpu->midr = ARM_CPUID_ARM1176; cpu->reset_fpsid = 0x410120b5; + cpu->mvfr0 = 0x11111111; + cpu->mvfr1 = 0x00000000; arm_cpu_postconfig_init(cpu); } @@ -167,6 +173,8 @@ static void arm11mpcore_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VAPA); cpu->midr = ARM_CPUID_ARM11MPCORE; cpu->reset_fpsid = 0x410120b4; + cpu->mvfr0 = 0x11111111; + cpu->mvfr1 = 0x00000000; arm_cpu_postconfig_init(cpu); } @@ -188,6 +196,8 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); cpu->midr = ARM_CPUID_CORTEXA8; cpu->reset_fpsid = 0x410330c0; + cpu->mvfr0 = 0x11110222; + cpu->mvfr1 = 0x00011100; arm_cpu_postconfig_init(cpu); } @@ -206,6 +216,8 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->midr = ARM_CPUID_CORTEXA9; cpu->reset_fpsid = 0x41033090; + cpu->mvfr0 = 0x11110222; + cpu->mvfr1 = 0x01111111; arm_cpu_postconfig_init(cpu); } @@ -222,6 +234,8 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); cpu->midr = ARM_CPUID_CORTEXA15; cpu->reset_fpsid = 0x410430f0; + cpu->mvfr0 = 0x10110222; + cpu->mvfr1 = 0x11111111; arm_cpu_postconfig_init(cpu); } diff --git a/target-arm/helper.c b/target-arm/helper.c index c7cde4f..aeffd6b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -73,31 +73,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) * for 1136_r2 (in particular r0p2 does not actually implement most * of the ID registers). */ - env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; - env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: - env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; - env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: - env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; - env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: - env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; - env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); env->cp15.c0_cachetype = 0x82048004; @@ -108,8 +100,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: - env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; - env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); env->cp15.c0_cachetype = 0x80038003; @@ -119,8 +109,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA15: - env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222; - env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111; memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t)); env->cp15.c0_cachetype = 0x8444c004; @@ -195,6 +183,8 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c15_config_base_address = tmp; env->cp15.c0_cpuid = cpu->midr; env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; + env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; + env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; -- 1.7.1