From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33044) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDbJG-0001db-7y for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:52:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDbJ9-0000CK-Sh for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:52:05 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:41204) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDbJ9-0000Bv-Kq for qemu-devel@nongnu.org; Fri, 30 Mar 2012 08:51:59 -0400 From: Peter Maydell Date: Fri, 30 Mar 2012 13:51:44 +0100 Message-Id: <1333111910-3641-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1333111910-3641-1-git-send-email-peter.maydell@linaro.org> References: <1333111910-3641-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paul Brook , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= Move the iWMMXT wCID reset to cpu_state_reset(). Since we use the same value for all CPUs with this feature (with the major/minor revision fields set to the QEMU specific 'Q' value) there's no need to create an ARMCPU field just for this. Signed-off-by: Peter Maydell --- target-arm/helper.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index e3e019a..0bc5529 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -122,7 +122,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C5: - env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; break; case ARM_CPUID_SA1100: case ARM_CPUID_SA1110: @@ -162,6 +161,10 @@ void cpu_state_reset(CPUARMState *env) env->cp15.c0_cachetype = cpu->ctr; env->cp15.c1_sys = cpu->reset_sctlr; + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; + } + #if defined (CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */ -- 1.7.1