From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:44745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDfUT-0002M9-8R for qemu-devel@nongnu.org; Fri, 30 Mar 2012 13:19:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDfUR-00062x-Ej for qemu-devel@nongnu.org; Fri, 30 Mar 2012 13:19:56 -0400 Received: from mail-qc0-f173.google.com ([209.85.216.173]:46041) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDfUR-00062I-8N for qemu-devel@nongnu.org; Fri, 30 Mar 2012 13:19:55 -0400 Received: by qcsc20 with SMTP id c20so505344qcs.4 for ; Fri, 30 Mar 2012 10:19:53 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 30 Mar 2012 13:16:36 -0400 Message-Id: <1333127797-8133-2-git-send-email-rth@twiddle.net> In-Reply-To: <1333127797-8133-1-git-send-email-rth@twiddle.net> References: <1333127797-8133-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 1/2] target-mips: Streamline indexed cp1 memory addressing. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net We've already eliminated both base and index being zero. --- target-mips/translate.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index a663b74..300d95e 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, } else if (index == 0) { gen_load_gpr(t0, base); } else { - gen_load_gpr(t0, index); - gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ -- 1.7.7.6