From: Michael Walle <michael@walle.cc>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>,
Michael Walle <michael@walle.cc>,
Anthony Liguori <anthony@codemonkey.ws>
Subject: [Qemu-devel] [PATCH 3/5] milkymist-sysctl: support for new core version
Date: Sun, 1 Apr 2012 20:37:34 +0200 [thread overview]
Message-ID: <1333305456-15415-4-git-send-email-michael@walle.cc> (raw)
In-Reply-To: <1333305456-15415-1-git-send-email-michael@walle.cc>
The new version introduces the following new registers:
- SoC clock frequency: read-only of system clock used on the SoC
- debug scratchpad: 8 bit scratchpad register
- debug write lock: write once register, without any function on QEMU
Signed-off-by: Michael Walle <michael@walle.cc>
---
hw/milkymist-sysctl.c | 26 +++++++++++++++++---------
1 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/hw/milkymist-sysctl.c b/hw/milkymist-sysctl.c
index a88548e..8878d2b 100644
--- a/hw/milkymist-sysctl.c
+++ b/hw/milkymist-sysctl.c
@@ -1,7 +1,7 @@
/*
* QEMU model of the Milkymist System Controller.
*
- * Copyright (c) 2010 Michael Walle <michael@walle.cc>
+ * Copyright (c) 2010-2012 Michael Walle <michael@walle.cc>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -39,20 +39,19 @@ enum {
};
enum {
- R_GPIO_IN = 0,
+ R_GPIO_IN = 0,
R_GPIO_OUT,
R_GPIO_INTEN,
- R_RESERVED0,
- R_TIMER0_CONTROL,
+ R_TIMER0_CONTROL = 4,
R_TIMER0_COMPARE,
R_TIMER0_COUNTER,
- R_RESERVED1,
- R_TIMER1_CONTROL,
+ R_TIMER1_CONTROL = 8,
R_TIMER1_COMPARE,
R_TIMER1_COUNTER,
- R_RESERVED2,
- R_RESERVED3,
- R_ICAP,
+ R_ICAP = 16,
+ R_DBG_SCRATCHPAD = 20,
+ R_DBG_WRITE_LOCK,
+ R_CLK_FREQUENCY = 29,
R_CAPABILITIES,
R_SYSTEM_ID,
R_MAX
@@ -116,6 +115,9 @@ static uint64_t sysctl_read(void *opaque, target_phys_addr_t addr,
case R_TIMER1_CONTROL:
case R_TIMER1_COMPARE:
case R_ICAP:
+ case R_DBG_SCRATCHPAD:
+ case R_DBG_WRITE_LOCK:
+ case R_CLK_FREQUENCY:
case R_CAPABILITIES:
case R_SYSTEM_ID:
r = s->regs[addr];
@@ -145,6 +147,7 @@ static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value,
case R_GPIO_INTEN:
case R_TIMER0_COUNTER:
case R_TIMER1_COUNTER:
+ case R_DBG_SCRATCHPAD:
s->regs[addr] = value;
break;
case R_TIMER0_COMPARE:
@@ -182,11 +185,15 @@ static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value,
case R_ICAP:
sysctl_icap_write(s, value);
break;
+ case R_DBG_WRITE_LOCK:
+ s->regs[addr] = 1;
+ break;
case R_SYSTEM_ID:
qemu_system_reset_request();
break;
case R_GPIO_IN:
+ case R_CLK_FREQUENCY:
case R_CAPABILITIES:
error_report("milkymist_sysctl: write to read-only register 0x"
TARGET_FMT_plx, addr << 2);
@@ -253,6 +260,7 @@ static void milkymist_sysctl_reset(DeviceState *d)
/* defaults */
s->regs[R_ICAP] = ICAP_READY;
s->regs[R_SYSTEM_ID] = s->systemid;
+ s->regs[R_CLK_FREQUENCY] = s->freq_hz;
s->regs[R_CAPABILITIES] = s->capabilities;
s->regs[R_GPIO_IN] = s->strappings;
}
--
1.7.2.5
next prev parent reply other threads:[~2012-04-01 18:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-01 18:37 [Qemu-devel] [PULL v2 0/5] lm32 fixes and additions Michael Walle
2012-04-01 18:37 ` [Qemu-devel] [PATCH 1/5] tests: fix out-of-tree building for lm32 target Michael Walle
2012-04-01 18:37 ` [Qemu-devel] [PATCH 2/5] target-lm32: init tcg only if available Michael Walle
2012-04-01 18:37 ` Michael Walle [this message]
2012-04-01 18:37 ` [Qemu-devel] [PATCH 4/5] target-lm32: add simple disassembler Michael Walle
2012-04-01 18:37 ` [Qemu-devel] [PATCH 5/5] milkymist-vgafb: add missing register Michael Walle
2012-04-01 19:10 ` [Qemu-devel] [PULL v2 0/5] lm32 fixes and additions Blue Swirl
-- strict thread matches above, loose matches on Subject: below --
2012-03-31 18:40 [Qemu-devel] [PULL " Michael Walle
2012-03-31 18:40 ` [Qemu-devel] [PATCH 3/5] milkymist-sysctl: support for new core version Michael Walle
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