From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35278) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SEeqL-0003sw-9M for qemu-devel@nongnu.org; Mon, 02 Apr 2012 06:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SEeqF-0003jZ-2z for qemu-devel@nongnu.org; Mon, 02 Apr 2012 06:50:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:32568) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SEeqE-0003jF-Rc for qemu-devel@nongnu.org; Mon, 02 Apr 2012 06:50:31 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q32AoTWg023804 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Mon, 2 Apr 2012 06:50:29 -0400 From: "Daniel P. Berrange" Date: Mon, 2 Apr 2012 11:50:13 +0100 Message-Id: <1333363816-1691-7-git-send-email-berrange@redhat.com> In-Reply-To: <1333363816-1691-1-git-send-email-berrange@redhat.com> References: <1333363816-1691-1-git-send-email-berrange@redhat.com> Subject: [Qemu-devel] [PATCH 6/9] Fix bit test to use & instead of && and enable -Wlogical-op warning List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Daniel P. Berrange" * configure: Enable -Wlogical-op * hw/exynos4210_uart.c: s/&&/&/ Signed-off-by: Daniel P. Berrange --- configure | 1 + hw/exynos4210_uart.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 524458c..8ee6cdb 100755 --- a/configure +++ b/configure @@ -1192,6 +1192,7 @@ gcc_flags="$gcc_flags -Wpragmas" gcc_flags="$gcc_flags -Wtrampolines" gcc_flags="$gcc_flags -Wmissing-parameter-type" gcc_flags="$gcc_flags -Wuninitialized" +gcc_flags="$gcc_flags -Wlogical-op" cat > $TMPC << EOF int main(void) { return 0; } diff --git a/hw/exynos4210_uart.c b/hw/exynos4210_uart.c index 73a9c18..4b20105 100644 --- a/hw/exynos4210_uart.c +++ b/hw/exynos4210_uart.c @@ -246,7 +246,7 @@ static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s) uint32_t level = 0; uint32_t reg; - reg = (s->reg[I_(UFCON)] && UFCON_Tx_FIFO_TRIGGER_LEVEL) >> + reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; switch (s->channel) { @@ -277,7 +277,7 @@ static void exynos4210_uart_update_irq(Exynos4210UartState *s) */ if (s->reg[I_(UFCON)] && UFCON_FIFO_ENABLE) { - uint32_t count = (s->reg[I_(UFSTAT)] && UFSTAT_Tx_FIFO_COUNT) >> + uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> UFSTAT_Tx_FIFO_COUNT_SHIFT; if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { -- 1.7.7.6