From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:50253) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SP8vQ-0005iL-IC for qemu-devel@nongnu.org; Tue, 01 May 2012 04:59:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SP8vN-0007lm-4S for qemu-devel@nongnu.org; Tue, 01 May 2012 04:59:12 -0400 From: Alexander Graf Date: Tue, 1 May 2012 10:58:54 +0200 Message-Id: <1335862740-17408-3-git-send-email-agraf@suse.de> In-Reply-To: <1335862740-17408-1-git-send-email-agraf@suse.de> References: <1335862740-17408-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 2/8] PPC: Fix up e500 cache size setting List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel Developers Cc: blauwirbel@gmail.com, qemu-ppc@nongnu.org When initializing the e500 code, we need to expose its cache line size for user and system mode, while the mmu details are only interesting for system emulation. Split the 2 switch statements apart, allowing us to #ifdef out the mmu parts for user mode emulation while keeping all cache information consistent. Signed-off-by: Alexander Graf --- target-ppc/translate_init.c | 26 ++++++++++++++------------ 1 files changed, 14 insertions(+), 12 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index ba4b84d..6f61175 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -4461,33 +4461,36 @@ static void init_proc_e500 (CPUPPCState *env, int version) &spr_read_spefscr, &spr_write_spefscr, &spr_read_spefscr, &spr_write_spefscr, 0x00000000); +#if !defined(CONFIG_USER_ONLY) /* Memory management */ -#if defined(CONFIG_USER_ONLY) - env->dcache_line_size = 32; - env->icache_line_size = 32; -#else /* !defined(CONFIG_USER_ONLY) */ env->nb_pids = 3; env->nb_ways = 2; env->id_tlbs = 0; switch (version) { case fsl_e500v1: - /* e500v1 */ tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); - env->dcache_line_size = 32; - env->icache_line_size = 32; break; case fsl_e500v2: - /* e500v2 */ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); - env->dcache_line_size = 32; - env->icache_line_size = 32; break; case fsl_e500mc: - /* e500mc */ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); + break; + default: + cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); + } +#endif + /* Cache sizes */ + switch (version) { + case fsl_e500v1: + case fsl_e500v2: + env->dcache_line_size = 32; + env->icache_line_size = 32; + break; + case fsl_e500mc: env->dcache_line_size = 64; env->icache_line_size = 64; l1cfg0 |= 0x1000000; /* 64 byte cache block size */ @@ -4495,7 +4498,6 @@ static void init_proc_e500 (CPUPPCState *env, int version) default: cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } -#endif gen_spr_BookE206(env, 0x000000DF, tlbncfg); /* XXX : not implemented */ spr_register(env, SPR_HID0, "HID0", -- 1.6.0.2