From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Paul Brook" <paul@codesourcery.com>,
"Andreas Färber" <afaerber@suse.de>,
patches@linaro.org
Subject: [Qemu-devel] [PATCH 3/9] hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset
Date: Wed, 2 May 2012 18:12:06 +0100 [thread overview]
Message-ID: <1335978732-32559-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org>
Move the NVIC specific bits of reset to the NVIC's own
reset function, rather than using ifdefs in the common
arm_gic reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm_gic.c | 10 ----------
hw/armv7m_nvic.c | 7 +++++++
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 2d8ceb8..3293ae4 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -743,23 +743,13 @@ static void gic_reset(DeviceState *dev)
s->current_pending[i] = 1023;
s->running_irq[i] = 1023;
s->running_priority[i] = 0x100;
-#ifdef NVIC
- /* The NVIC doesn't have per-cpu interfaces, so enable by default. */
- s->cpu_enabled[i] = 1;
-#else
s->cpu_enabled[i] = 0;
-#endif
}
for (i = 0; i < 16; i++) {
GIC_SET_ENABLED(i, ALL_CPU_MASK);
GIC_SET_TRIGGER(i);
}
-#ifdef NVIC
- /* The NVIC is always enabled. */
- s->enabled = 1;
-#else
s->enabled = 0;
-#endif
}
static void gic_save(QEMUFile *f, void *opaque)
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 99a87a2..653c011 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -382,6 +382,13 @@ static void armv7m_nvic_reset(DeviceState *dev)
{
nvic_state *s = FROM_SYSBUSGIC(nvic_state, sysbus_from_qdev(dev));
gic_reset(&s->gic.busdev.qdev);
+ /* Common GIC reset resets to disabled; the NVIC doesn't have
+ * per-CPU interfaces so mark our non-existent CPU interface
+ * as enabled by default.
+ */
+ s->gic.cpu_enabled[0] = 1;
+ /* The NVIC as a whole is always enabled. */
+ s->gic.enabled = 1;
systick_reset(s);
}
--
1.7.1
next prev parent reply other threads:[~2012-05-02 17:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-02 17:12 [Qemu-devel] [PATCH 0/9] disentangle NVIC from ARM GIC Peter Maydell
2012-05-02 17:12 ` [Qemu-devel] [PATCH 1/9] hw/arm_gic: Remove NVIC ifdefs from gic_state struct Peter Maydell
2012-05-18 12:55 ` Andreas Färber
2012-05-02 17:12 ` [Qemu-devel] [PATCH 2/9] hw/arm_gic: Remove the special casing of NCPU for the NVIC Peter Maydell
2012-05-18 13:01 ` Andreas Färber
2012-05-18 13:21 ` Peter Maydell
2012-05-02 17:12 ` Peter Maydell [this message]
2012-05-02 17:12 ` [Qemu-devel] [PATCH 4/9] hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers Peter Maydell
2012-05-02 17:12 ` [Qemu-devel] [PATCH 5/9] hw/arm_gic: Add qdev property for GIC revision Peter Maydell
2012-05-02 17:12 ` [Qemu-devel] [PATCH 6/9] hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor Peter Maydell
2012-05-02 17:12 ` [Qemu-devel] [PATCH 7/9] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting Peter Maydell
2012-05-02 17:12 ` [Qemu-devel] [PATCH 8/9] hw/arm_gic: Move CPU interface memory region setup into arm_gic_init Peter Maydell
2012-05-02 17:12 ` [Qemu-devel] [PATCH 9/9] hw/armv7m_nvic: Make the NVIC a freestanding class Peter Maydell
2012-05-18 12:49 ` [Qemu-devel] [PATCH 0/9] disentangle NVIC from ARM GIC Peter Maydell
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