From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55753) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SPd6M-0002GI-7G for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SPd6J-0002WO-GJ for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:29 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:33531) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SPd6J-0002UL-8R for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:27 -0400 From: Peter Maydell Date: Wed, 2 May 2012 18:12:06 +0100 Message-Id: <1335978732-32559-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 3/9] hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Move the NVIC specific bits of reset to the NVIC's own reset function, rather than using ifdefs in the common arm_gic reset. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 10 ---------- hw/armv7m_nvic.c | 7 +++++++ 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 2d8ceb8..3293ae4 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -743,23 +743,13 @@ static void gic_reset(DeviceState *dev) s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; -#ifdef NVIC - /* The NVIC doesn't have per-cpu interfaces, so enable by default. */ - s->cpu_enabled[i] = 1; -#else s->cpu_enabled[i] = 0; -#endif } for (i = 0; i < 16; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); GIC_SET_TRIGGER(i); } -#ifdef NVIC - /* The NVIC is always enabled. */ - s->enabled = 1; -#else s->enabled = 0; -#endif } static void gic_save(QEMUFile *f, void *opaque) diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 99a87a2..653c011 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -382,6 +382,13 @@ static void armv7m_nvic_reset(DeviceState *dev) { nvic_state *s = FROM_SYSBUSGIC(nvic_state, sysbus_from_qdev(dev)); gic_reset(&s->gic.busdev.qdev); + /* Common GIC reset resets to disabled; the NVIC doesn't have + * per-CPU interfaces so mark our non-existent CPU interface + * as enabled by default. + */ + s->gic.cpu_enabled[0] = 1; + /* The NVIC as a whole is always enabled. */ + s->gic.enabled = 1; systick_reset(s); } -- 1.7.1