From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55749) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SPd6M-0002FT-0v for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SPd6G-0002Vo-SO for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:29 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:33531) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SPd6G-0002UL-Kn for qemu-devel@nongnu.org; Wed, 02 May 2012 13:12:24 -0400 From: Peter Maydell Date: Wed, 2 May 2012 18:12:10 +0100 Message-Id: <1335978732-32559-8-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 7/9] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Make the minor tweaks to interrupt numbering used by the NVIC a runtime setting rather than a compile time one, so we can drop more NVIC ifdefs. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index a6e2431..c288bc5 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -36,13 +36,9 @@ do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0) #define DPRINTF(fmt, ...) do {} while(0) #endif -#ifdef NVIC /* The NVIC has 16 internal vectors. However these are not exposed through the normal GIC interface. */ -#define GIC_BASE_IRQ 32 -#else -#define GIC_BASE_IRQ 0 -#endif +#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0) static const uint8_t gic_id[] = { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 @@ -839,7 +835,6 @@ static void gic_init(gic_state *s, int num_irq) } i = s->num_irq - GIC_INTERNAL; -#ifndef NVIC /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. * GPIO array layout is thus: * [0..N-1] SPIs @@ -847,8 +842,9 @@ static void gic_init(gic_state *s, int num_irq) * [N+32..N+63] PPIs for CPU 1 * ... */ - i += (GIC_INTERNAL * s->num_cpu); -#endif + if (s->revision != REV_NVIC) { + i += (GIC_INTERNAL * s->num_cpu); + } qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(&s->busdev, &s->parent_irq[i]); -- 1.7.1