From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:60266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SR3VJ-0000rp-SA for qemu-devel@nongnu.org; Sun, 06 May 2012 11:36:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SR3VH-0000ml-Q5 for qemu-devel@nongnu.org; Sun, 06 May 2012 11:36:09 -0400 Received: from cantor2.suse.de ([195.135.220.15]:55353 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SR3VH-0000m2-HO for qemu-devel@nongnu.org; Sun, 06 May 2012 11:36:07 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 6 May 2012 17:34:41 +0200 Message-Id: <1336318514-30906-42-git-send-email-afaerber@suse.de> In-Reply-To: <1336318514-30906-1-git-send-email-afaerber@suse.de> References: <1336318514-30906-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH for-next 41/74] target-lm32: Let cpu_lm32_init() return LM32CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Michael Walle , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Anthony Liguori Make the include paths for cpu-qom.h consistent to allow using LM32CPU in cpu.h. Let cpu_init() return CPULM32State for backwards compatibility. Signed-off-by: Andreas F=C3=A4rber --- target-lm32/cpu.c | 2 +- target-lm32/cpu.h | 4 ++-- target-lm32/helper.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 48a5fe3..caa4834 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -18,7 +18,7 @@ * */ =20 -#include "cpu-qom.h" +#include "cpu.h" #include "qemu-common.h" =20 =20 diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 422a55b..642f19b 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -186,7 +186,7 @@ struct CPULM32State { =20 #include "cpu-qom.h" =20 -CPULM32State *cpu_lm32_init(const char *cpu_model); +LM32CPU *cpu_lm32_init(const char *cpu_model); void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf); int cpu_lm32_exec(CPULM32State *s); void cpu_lm32_close(CPULM32State *s); @@ -200,7 +200,7 @@ void lm32_translate_init(void); void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value); =20 #define cpu_list cpu_lm32_list -#define cpu_init cpu_lm32_init +#define cpu_init(model) (&cpu_lm32_init(model)->env) #define cpu_exec cpu_lm32_exec #define cpu_gen_code cpu_lm32_gen_code #define cpu_signal_handler cpu_lm32_signal_handler diff --git a/target-lm32/helper.c b/target-lm32/helper.c index d0bc193..3b1cee7 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -192,7 +192,7 @@ static uint32_t cfg_by_def(const LM32Def *def) return cfg; } =20 -CPULM32State *cpu_lm32_init(const char *cpu_model) +LM32CPU *cpu_lm32_init(const char *cpu_model) { LM32CPU *cpu; CPULM32State *env; @@ -219,7 +219,7 @@ CPULM32State *cpu_lm32_init(const char *cpu_model) lm32_translate_init(); } =20 - return env; + return cpu; } =20 /* Some soc ignores the MSB on the address bus. Thus creating a shadow m= emory --=20 1.7.7