[Qemu-devel] [PULL for-1.1] target-arm queue

[Qemu-devel] [PULL for-1.1] target-arm queue

[Peter Maydell]

This is a pullreq for a single target-arm patch which I think worth
putting into 1.1. The bug has been in qemu for some time but it is
a trivial and obvious one-line fix. Please pull.

thanks
-- PMM

The following changes since commit 847c25d01cbe8e4fe457a7426f82daaaf3287aae:

  hw/ac97: Mask out the EAPD bit on Powerdown Ctrl/Stat writes (2012-05-07 16:31:40 +0400)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Matt Craighead (1):
      target-arm: When setting FPSCR.QC, don't clear other FPSCR bits

 target-arm/neon_helper.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

[Qemu-devel] [PATCH] target-arm: When setting FPSCR.QC, don't clear other FPSCR bits

[Peter Maydell]

From: Matt Craighead <mjcraighead@gmail.com>

This patch fixes a bug affecting a variety of Neon instructions, such as
VQADD.

Signed-off-by: Matt Craighead <mjcraighead@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/neon_helper.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c
index 1e02d61..e0b9dbf 100644
--- a/target-arm/neon_helper.c
+++ b/target-arm/neon_helper.c
@@ -16,7 +16,7 @@
 #define SIGNBIT (uint32_t)0x80000000
 #define SIGNBIT64 ((uint64_t)1 << 63)
 
-#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] = CPSR_Q
+#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
 
 #define NEON_TYPE1(name, type) \
 typedef struct \
-- 
1.7.1