[Qemu-devel] [PATCH v2 for-1.1 0/4] tcg/ppc: AREG0 support and Darwin fixes

[Qemu-devel] [PATCH v2 for-1.1 0/4] tcg/ppc: AREG0 support and Darwin fixes

[Andreas Färber]

Hello malc,

Here's an updated series to fix AREG0 and ppc build.

Debian/sparc fsck on Darwin/ppc now succeeds. No regressions noticed with
Debian/sparc, HelenOS/sparc64, Haiku/i386, Haiku/x86_64.

Regards,
Andreas

Cc: malc <av1474@comtv.ru>
Cc: Alexander Graf <agraf@suse.de>

v1 -> v2:
* Drop _CALL_DARWIN fix that malc doesn't accept (_CALL_DARWIN being reserved).
* Fix a register clobbering issue with 64-bit loads in non-AREG0 path.
* Split register numbering and alignment adjustments off from AREG0 support.
* Address register clobbering for AREG0 aligned and unaligned paths.

Andreas Färber (4):
  tcg/ppc: Do not overwrite lower address word on Darwin and AIX
  tcg/ppc: Don't hardcode register numbers
  tcg/ppc: Clobber r5 for 64-bit qemu_ld
  tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode

 tcg/ppc/tcg-target.c |   69 +++++++++++++++++++++++++++++++++++++++-----------
 1 files changed, 54 insertions(+), 15 deletions(-)

-- 
1.7.7

[Qemu-devel] [PATCH v2 for-1.1 1/4] tcg/ppc: Do not overwrite lower address word on Darwin and AIX

[Andreas Färber]

From: Andreas Färber <andreas.faerber@web.de>

For targets where TARGET_LONG_BITS != 32, i.e. 64-bit guests,
addr_reg is moved to r4. For hosts without TCG_TARGET_CALL_ALIGN_ARGS
either data_reg2 or data_reg or a masked version thereof would overwrite
r4. Place it in r5 instead, matching TCG_TARGET_CALL_ALIGN_ARGS hosts.

This fixes immediate crashes of 64-bit guests observed on Darwin/ppc but
not on Darwin/ppc64.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 tcg/ppc/tcg-target.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index dc40716..4b85c89 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -816,11 +816,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
 #else
     tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
     tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
-#ifdef TCG_TARGET_CALL_ALIGN_ARGS
     ir = 5;
-#else
-    ir = 4;
-#endif
 #endif
 
     switch (opc) {
-- 
1.7.7

[Qemu-devel] [PATCH v2 for-1.1 2/4] tcg/ppc: Don't hardcode register numbers

[Andreas Färber]

Also assure i64 alignment where necessary.

Alignment code optimization suggested by malc.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 tcg/ppc/tcg-target.c |   29 +++++++++++++++++------------
 1 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 4b85c89..b4e0466 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -552,7 +552,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
 {
     int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap;
 #ifdef CONFIG_SOFTMMU
-    int mem_index, s_bits, r2;
+    int mem_index, s_bits, r2, ir;
     void *label1_ptr, *label2_ptr;
 #if TARGET_LONG_BITS == 64
     int addr_reg2;
@@ -614,14 +614,17 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
 #endif
 
     /* slow path */
+    ir = 3;
 #if TARGET_LONG_BITS == 32
-    tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg);
-    tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
+    tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #else
-    tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
-    tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
-    tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+    ir |= 1;
+#endif
+    tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg2);
+    tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #endif
+    tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
 
     tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
     switch (opc) {
@@ -810,13 +813,15 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
 #endif
 
     /* slow path */
+    ir = 3;
 #if TARGET_LONG_BITS == 32
-    tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg);
-    ir = 4;
+    tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #else
-    tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
-    tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
-    ir = 5;
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+    ir |= 1;
+#endif
+    tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg2);
+    tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #endif
 
     switch (opc) {
@@ -841,7 +846,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
         break;
     case 3:
 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
-        ir = 5;
+        ir |= 1;
 #endif
         tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2);
         tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
-- 
1.7.7

[Qemu-devel] [PATCH v2 for-1.1 3/4] tcg/ppc: Clobber r5 for 64-bit qemu_ld

[Andreas Färber]

This accounts for the additional addr_reg2 register.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 tcg/ppc/tcg-target.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index b4e0466..20888e2 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -244,6 +244,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
+#if TARGET_LONG_BITS == 64
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
+#endif
         break;
     case 'K':                   /* qemu_st[8..32] constraint */
         ct->ct |= TCG_CT_REG;
-- 
1.7.7

[Qemu-devel] [PATCH v2 for-1.1 4/4] tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode

[Andreas Färber]

Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
based on patches by malc.

Also adjust the registers clobbered, based on patch by Alex.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 tcg/ppc/tcg-target.c |   37 ++++++++++++++++++++++++++++++++++++-
 1 files changed, 36 insertions(+), 1 deletions(-)

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 20888e2..ca84aba 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -244,9 +244,19 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
         tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
+#ifdef CONFIG_TCG_PASS_AREG0
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
+#if TARGET_LONG_BITS == 64
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
+#endif
+#endif
+#else /* !AREG0 */
 #if TARGET_LONG_BITS == 64
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
 #endif
+#endif
         break;
     case 'K':                   /* qemu_st[8..32] constraint */
         ct->ct |= TCG_CT_REG;
@@ -254,9 +264,19 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
+#ifdef CONFIG_TCG_PASS_AREG0
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
+#if TARGET_LONG_BITS == 64
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
+#endif
+#endif
+#else /* !AREG0 */
 #if TARGET_LONG_BITS == 64
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
 #endif
+#endif
         break;
     case 'M':                   /* qemu_st64 constraint */
         ct->ct |= TCG_CT_REG;
@@ -266,6 +286,12 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
+#if defined(CONFIG_TCG_PASS_AREG0)
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
+#endif
+#endif
         break;
 #else
     case 'L':
@@ -512,7 +538,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
 #include "../../softmmu_defs.h"
 
 #ifdef CONFIG_TCG_PASS_AREG0
-#error CONFIG_TCG_PASS_AREG0 is not supported
 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
    int mmu_idx) */
 static const void * const qemu_ld_helpers[4] = {
@@ -617,7 +642,12 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
 #endif
 
     /* slow path */
+#ifdef CONFIG_TCG_PASS_AREG0
+    tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
+    ir = 4;
+#else
     ir = 3;
+#endif
 #if TARGET_LONG_BITS == 32
     tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #else
@@ -816,7 +846,12 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
 #endif
 
     /* slow path */
+#ifdef CONFIG_TCG_PASS_AREG0
+    tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
+    ir = 4;
+#else
     ir = 3;
+#endif
 #if TARGET_LONG_BITS == 32
     tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #else
-- 
1.7.7

Re: [Qemu-devel] [PATCH v2 for-1.1 4/4] tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode

[malc]

On Wed, 9 May 2012, Andreas F?rber wrote:

> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
> based on patches by malc.
> 
> Also adjust the registers clobbered, based on patch by Alex.

Alexander, my head is splitting now, so i can not calculate things inside
it, aren't we reserving skipped registers in some circumstances?

[..snip..]

-- 
mailto:av1474@comtv.ru

Re: [Qemu-devel] [PATCH v2 for-1.1 4/4] tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode

[Andreas Färber]

Am 09.05.2012 02:43, schrieb malc:
> On Wed, 9 May 2012, Andreas F?rber wrote:
> 
>> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
>> based on patches by malc.
>>
>> Also adjust the registers clobbered, based on patch by Alex.
> 
> Alexander, my head is splitting now, so i can not calculate things inside
> it, aren't we reserving skipped registers in some circumstances?

Yes, we are. The original code did, and Alex found it too complicated
for the immediate build fix when I suggested it. As you can see, I've
already split up into AREG0 and non #ifdef paths because it got too
unreadable when having one line with multiple or'ed #if conditions.

Optimizations we can still do when the build is restored.

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH v2 for-1.1 4/4] tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode

[Alexander Graf]

On 05/09/2012 02:43 AM, malc wrote:
> On Wed, 9 May 2012, Andreas F?rber wrote:
>
>> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
>> based on patches by malc.
>>
>> Also adjust the registers clobbered, based on patch by Alex.
> Alexander, my head is splitting now, so i can not calculate things inside
> it, aren't we reserving skipped registers in some circumstances?

Yes we are. And I don't think we should care :).


Alex

Re: [Qemu-devel] [PATCH v2 for-1.1 4/4] tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode

[Alexander Graf]

On 05/09/2012 02:28 AM, Andreas Färber wrote:
> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
> based on patches by malc.
>
> Also adjust the registers clobbered, based on patch by Alex.
>
> Signed-off-by: Andreas Färber<afaerber@suse.de>
> ---
>   tcg/ppc/tcg-target.c |   37 ++++++++++++++++++++++++++++++++++++-
>   1 files changed, 36 insertions(+), 1 deletions(-)
>
> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
> index 20888e2..ca84aba 100644
> --- a/tcg/ppc/tcg-target.c
> +++ b/tcg/ppc/tcg-target.c
> @@ -244,9 +244,19 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>           tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
> +#ifdef CONFIG_TCG_PASS_AREG0
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
> +#if TARGET_LONG_BITS == 64
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
> +#ifdef TCG_TARGET_CALL_ALIGN_ARGS
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
> +#endif
> +#endif
> +#else /* !AREG0 */
>   #if TARGET_LONG_BITS == 64
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>   #endif
> +#endif
>           break;
>       case 'K':                   /* qemu_st[8..32] constraint */
>           ct->ct |= TCG_CT_REG;
> @@ -254,9 +264,19 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
> +#ifdef CONFIG_TCG_PASS_AREG0
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
> +#if TARGET_LONG_BITS == 64
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
> +#ifdef TCG_TARGET_CALL_ALIGN_ARGS
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
> +#endif
> +#endif
> +#else /* !AREG0 */
>   #if TARGET_LONG_BITS == 64
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>   #endif
> +#endif
>           break;
>       case 'M':                   /* qemu_st64 constraint */
>           ct->ct |= TCG_CT_REG;
> @@ -266,6 +286,12 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
> +#if defined(CONFIG_TCG_PASS_AREG0)
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
> +#ifdef TCG_TARGET_CALL_ALIGN_ARGS
> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
> +#endif
> +#endif
>           break;
>   #else
>       case 'L':
> @@ -512,7 +538,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
>   #include "../../softmmu_defs.h"
>
>   #ifdef CONFIG_TCG_PASS_AREG0
> -#error CONFIG_TCG_PASS_AREG0 is not supported
>   /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>      int mmu_idx) */
>   static const void * const qemu_ld_helpers[4] = {
> @@ -617,7 +642,12 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
>   #endif
>
>       /* slow path */
> +#ifdef CONFIG_TCG_PASS_AREG0
> +    tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
> +    ir = 4;
> +#else
>       ir = 3;
> +#endif

I liked your "start ir with 3 and only ir++ from then on" way of doing 
this better.

ir = 3;
#ifdef ...
    tcg_out_mov(,,, ir++);
#endif

>   #if TARGET_LONG_BITS == 32
>       tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
>   #else
> @@ -816,7 +846,12 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
>   #endif
>
>       /* slow path */
> +#ifdef CONFIG_TCG_PASS_AREG0
> +    tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
> +    ir = 4;
> +#else
>       ir = 3;
> +#endif

Same here


Alex

Re: [Qemu-devel] [PATCH v2 for-1.1 4/4] tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode

[Andreas Färber]

Am 09.05.2012 12:27, schrieb Alexander Graf:
> On 05/09/2012 02:28 AM, Andreas Färber wrote:
>> Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
>> based on patches by malc.
>>
>> Also adjust the registers clobbered, based on patch by Alex.
>>
>> Signed-off-by: Andreas Färber<afaerber@suse.de>
>> ---
>>   tcg/ppc/tcg-target.c |   37 ++++++++++++++++++++++++++++++++++++-
>>   1 files changed, 36 insertions(+), 1 deletions(-)
>>
>> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
>> index 20888e2..ca84aba 100644
>> --- a/tcg/ppc/tcg-target.c
>> +++ b/tcg/ppc/tcg-target.c
>> @@ -244,9 +244,19 @@ static int
>> target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>>           tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
>> +#ifdef CONFIG_TCG_PASS_AREG0
>> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>> +#if TARGET_LONG_BITS == 64
>> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>> +#ifdef TCG_TARGET_CALL_ALIGN_ARGS
>> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
>> +#endif
>> +#endif
>> +#else /* !AREG0 */
>>   #if TARGET_LONG_BITS == 64
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>>   #endif
>> +#endif
>>           break;
>>       case 'K':                   /* qemu_st[8..32] constraint */
>>           ct->ct |= TCG_CT_REG;
>> @@ -254,9 +264,19 @@ static int
>> target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>> +#ifdef CONFIG_TCG_PASS_AREG0
>> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>> +#if TARGET_LONG_BITS == 64
>> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
>> +#ifdef TCG_TARGET_CALL_ALIGN_ARGS
>> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
>> +#endif
>> +#endif
>> +#else /* !AREG0 */
>>   #if TARGET_LONG_BITS == 64
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>>   #endif
>> +#endif
>>           break;
>>       case 'M':                   /* qemu_st64 constraint */
>>           ct->ct |= TCG_CT_REG;
>> @@ -266,6 +286,12 @@ static int
>> target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
>>           tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
>> +#if defined(CONFIG_TCG_PASS_AREG0)
>> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
>> +#ifdef TCG_TARGET_CALL_ALIGN_ARGS
>> +        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
>> +#endif
>> +#endif
>>           break;
>>   #else
>>       case 'L':
>> @@ -512,7 +538,6 @@ static void tcg_out_call (TCGContext *s,
>> tcg_target_long arg, int const_arg)
>>   #include "../../softmmu_defs.h"
>>
>>   #ifdef CONFIG_TCG_PASS_AREG0
>> -#error CONFIG_TCG_PASS_AREG0 is not supported
>>   /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
>>      int mmu_idx) */
>>   static const void * const qemu_ld_helpers[4] = {
>> @@ -617,7 +642,12 @@ static void tcg_out_qemu_ld (TCGContext *s, const
>> TCGArg *args, int opc)
>>   #endif
>>
>>       /* slow path */
>> +#ifdef CONFIG_TCG_PASS_AREG0
>> +    tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
>> +    ir = 4;
>> +#else
>>       ir = 3;
>> +#endif
> 
> I liked your "start ir with 3 and only ir++ from then on" way of doing
> this better.
> 
> ir = 3;
> #ifdef ...
>    tcg_out_mov(,,, ir++);
> #endif

This didn't change from v1, but I can update.

Andreas

> 
>>   #if TARGET_LONG_BITS == 32
>>       tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
>>   #else
>> @@ -816,7 +846,12 @@ static void tcg_out_qemu_st (TCGContext *s, const
>> TCGArg *args, int opc)
>>   #endif
>>
>>       /* slow path */
>> +#ifdef CONFIG_TCG_PASS_AREG0
>> +    tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
>> +    ir = 4;
>> +#else
>>       ir = 3;
>> +#endif
> 
> Same here
> 
> 
> Alex

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH v2 for-1.1 0/4] tcg/ppc: AREG0 support and Darwin fixes

[malc]

On Wed, 9 May 2012, Andreas F?rber wrote:

> Hello malc,
> 
> Here's an updated series to fix AREG0 and ppc build.
> 
> Debian/sparc fsck on Darwin/ppc now succeeds. No regressions noticed with
> Debian/sparc, HelenOS/sparc64, Haiku/i386, Haiku/x86_64.
> 
> Regards,
> Andreas
> 
> Cc: malc <av1474@comtv.ru>
> Cc: Alexander Graf <agraf@suse.de>
> 

If Alexander is okay with this and you have tested it on SysV and Darwin
i'll apply it.

[..snip..]

-- 
mailto:av1474@comtv.ru

Re: [Qemu-devel] [PATCH v2 for-1.1 0/4] tcg/ppc: AREG0 support and Darwin fixes

[Andreas Färber]

Am 09.05.2012 02:33, schrieb malc:
> On Wed, 9 May 2012, Andreas F?rber wrote:
> 
>> Here's an updated series to fix AREG0 and ppc build.
>>
>> Debian/sparc fsck on Darwin/ppc now succeeds. No regressions noticed with
>> Debian/sparc, HelenOS/sparc64, Haiku/i386, Haiku/x86_64.
> 
> If Alexander is okay with this and you have tested it on SysV and Darwin
> i'll apply it.

Sorry, yes, I tested on both Linux and Darwin. On Darwin with my
_CALL_DARWIN patch on top, on Linux with a sun4m workaround.
No feedback from Alex on his test case yet.

Available for testing on my "tcg-osx-ppc" branch.

AREG0 ppc I've just patched (on my "ppc" branch), and Alex' kvm-ppc-next
kernel boots okay.

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH v2 for-1.1 0/4] tcg/ppc: AREG0 support and Darwin fixes

[Alexander Graf]

On 05/09/2012 02:33 AM, malc wrote:
> On Wed, 9 May 2012, Andreas F?rber wrote:
>
>> Hello malc,
>>
>> Here's an updated series to fix AREG0 and ppc build.
>>
>> Debian/sparc fsck on Darwin/ppc now succeeds. No regressions noticed with
>> Debian/sparc, HelenOS/sparc64, Haiku/i386, Haiku/x86_64.
>>
>> Regards,
>> Andreas
>>
>> Cc: malc<av1474@comtv.ru>
>> Cc: Alexander Graf<agraf@suse.de>
>>
> If Alexander is okay with this and you have tested it on SysV and Darwin
> i'll apply it.

Apart from the minor nitpick on the register numbering, I'm all for it! 
If you like, you can even apply the version we have now to get rc1 out 
and then apply another patch to fix my comment (and maybe the generous 
register reservation) later.


Alex