From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SRulP-0001Wn-7v for qemu-devel@nongnu.org; Tue, 08 May 2012 20:28:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SRulN-0000qS-63 for qemu-devel@nongnu.org; Tue, 08 May 2012 20:28:18 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 9 May 2012 02:28:10 +0200 Message-Id: <1336523290-6899-5-git-send-email-afaerber@suse.de> In-Reply-To: <1336523290-6899-1-git-send-email-afaerber@suse.de> References: <1336523290-6899-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 for-1.1 4/4] tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, agraf@suse.de, =?UTF-8?q?Andreas=20F=C3=A4rber?= Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3, based on patches by malc. Also adjust the registers clobbered, based on patch by Alex. Signed-off-by: Andreas F=C3=A4rber --- tcg/ppc/tcg-target.c | 37 ++++++++++++++++++++++++++++++++++++- 1 files changed, 36 insertions(+), 1 deletions(-) diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 20888e2..ca84aba 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -244,9 +244,19 @@ static int target_parse_constraint(TCGArgConstraint = *ct, const char **pct_str) tcg_regset_set32(ct->u.regs, 0, 0xffffffff); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); +#if TARGET_LONG_BITS =3D=3D 64 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); +#endif +#endif +#else /* !AREG0 */ #if TARGET_LONG_BITS =3D=3D 64 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); #endif +#endif break; case 'K': /* qemu_st[8..32] constraint */ ct->ct |=3D TCG_CT_REG; @@ -254,9 +264,19 @@ static int target_parse_constraint(TCGArgConstraint = *ct, const char **pct_str) tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); +#if TARGET_LONG_BITS =3D=3D 64 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8); +#endif +#endif +#else /* !AREG0 */ #if TARGET_LONG_BITS =3D=3D 64 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); #endif +#endif break; case 'M': /* qemu_st64 constraint */ ct->ct |=3D TCG_CT_REG; @@ -266,6 +286,12 @@ static int target_parse_constraint(TCGArgConstraint = *ct, const char **pct_str) tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); +#if defined(CONFIG_TCG_PASS_AREG0) + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8); +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9); +#endif +#endif break; #else case 'L': @@ -512,7 +538,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_l= ong arg, int const_arg) #include "../../softmmu_defs.h" =20 #ifdef CONFIG_TCG_PASS_AREG0 -#error CONFIG_TCG_PASS_AREG0 is not supported /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, int mmu_idx) */ static const void * const qemu_ld_helpers[4] =3D { @@ -617,7 +642,12 @@ static void tcg_out_qemu_ld (TCGContext *s, const TC= GArg *args, int opc) #endif =20 /* slow path */ +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0); + ir =3D 4; +#else ir =3D 3; +#endif #if TARGET_LONG_BITS =3D=3D 32 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); #else @@ -816,7 +846,12 @@ static void tcg_out_qemu_st (TCGContext *s, const TC= GArg *args, int opc) #endif =20 /* slow path */ +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0); + ir =3D 4; +#else ir =3D 3; +#endif #if TARGET_LONG_BITS =3D=3D 32 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); #else --=20 1.7.7