From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:50871) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSH2a-0001tT-BM for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SSH2X-0005k4-MT for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:31 -0400 Received: from cantor2.suse.de ([195.135.220.15]:35646 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSH2X-0005jI-Fz for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:29 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 10 May 2012 02:14:45 +0200 Message-Id: <1336608892-30501-68-git-send-email-afaerber@suse.de> In-Reply-To: <1336608892-30501-1-git-send-email-afaerber@suse.de> References: <1336608892-30501-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH next v2 67/74] mips_malta: Pass MIPSCPU to main_cpu_reset() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Allows us to use cpu_reset() in place of cpu_state_reset(). Signed-off-by: Andreas F=C3=A4rber --- hw/mips_malta.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index d81e8d5..dfd7b6b 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -751,8 +751,10 @@ static void malta_mips_config(CPUMIPSState *env) =20 static void main_cpu_reset(void *opaque) { - CPUMIPSState *env =3D opaque; - cpu_state_reset(env); + MIPSCPU *cpu =3D opaque; + CPUMIPSState *env =3D &cpu->env; + + cpu_reset(CPU(cpu)); =20 /* The bootloader does not need to be rewritten as it is located in = a read only location. The kernel location and the arguments table @@ -836,7 +838,7 @@ void mips_malta_init (ram_addr_t ram_size, /* Init internal devices */ cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, cpu); } env =3D first_cpu; =20 --=20 1.7.7