From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:54590) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ST0xF-0004XD-HL for qemu-devel@nongnu.org; Fri, 11 May 2012 21:17:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ST0xC-0002N8-SJ for qemu-devel@nongnu.org; Fri, 11 May 2012 21:17:05 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 12 May 2012 03:16:58 +0200 Message-Id: <1336785418-9439-3-git-send-email-afaerber@suse.de> In-Reply-To: <1336785418-9439-1-git-send-email-afaerber@suse.de> References: <1336785418-9439-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH for-1.1 2/2] tcg/ppc64: Fix CONFIG_TCG_PASS_AREG0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, agraf@suse.de, =?UTF-8?q?Andreas=20F=C3=A4rber?= In qemu_ld/st load the registers for the helper calls directly rather than rotating them around afterwards for AREG0. Also clobber the additional register. Signed-off-by: Andreas F=C3=A4rber --- tcg/ppc64/tcg-target.c | 32 ++++++++++++-------------------- 1 files changed, 12 insertions(+), 20 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0573a72..c800574 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -235,6 +235,9 @@ static int target_parse_constraint (TCGArgConstraint = *ct, const char **pct_str) tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5); +#endif #endif break; case 'S': /* qemu_st constraint */ @@ -244,6 +247,9 @@ static int target_parse_constraint (TCGArgConstraint = *ct, const char **pct_str) #ifdef CONFIG_SOFTMMU tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6); +#endif #endif break; case 'Z': @@ -670,18 +676,12 @@ static void tcg_out_qemu_ld (TCGContext *s, const T= CGArg *args, int opc) =20 /* slow path */ ir =3D 3; +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0); +#endif tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg); tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index); =20 -#ifdef CONFIG_TCG_PASS_AREG0 - /* XXX/FIXME: suboptimal */ - tcg_out_mov (s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], - tcg_target_call_iarg_regs[1]); - tcg_out_mov (s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - tcg_target_call_iarg_regs[0]); - tcg_out_mov (s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], - TCG_AREG0); -#endif tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1); =20 switch (opc) { @@ -827,21 +827,13 @@ static void tcg_out_qemu_st (TCGContext *s, const T= CGArg *args, int opc) =20 /* slow path */ ir =3D 3; +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0); +#endif tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg); tcg_out_rld (s, RLDICL, ir++, data_reg, 0, 64 - (1 << (3 + opc))); tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index); =20 -#ifdef CONFIG_TCG_PASS_AREG0 - /* XXX/FIXME: suboptimal */ - tcg_out_mov (s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], - tcg_target_call_iarg_regs[2]); - tcg_out_mov (s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], - tcg_target_call_iarg_regs[1]); - tcg_out_mov (s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - tcg_target_call_iarg_regs[0]); - tcg_out_mov (s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], - TCG_AREG0); -#endif tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1); =20 label2_ptr =3D s->code_ptr; --=20 1.7.7