From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35351) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STfQ3-0003Xf-6A for qemu-devel@nongnu.org; Sun, 13 May 2012 16:29:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1STfQ0-0004a5-M6 for qemu-devel@nongnu.org; Sun, 13 May 2012 16:29:30 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44192 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STfQ0-0004ZA-9s for qemu-devel@nongnu.org; Sun, 13 May 2012 16:29:28 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 13 May 2012 22:29:17 +0200 Message-Id: <1336940957-19686-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH qom-next] nseries: Rename n800_s::cpu to mpu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= omap_mpu_state_s::env was renamed to cpu while changing its type. With n800_s::cpu of type omap_mpu_state_s* this leads to s->cpu->cpu. Rename the field to "mpu" to avoid this ugliness. Signed-off-by: Andreas F=C3=A4rber Cc: Peter Maydell --- hw/nseries.c | 72 +++++++++++++++++++++++++++++-----------------------= ------ 1 files changed, 36 insertions(+), 36 deletions(-) diff --git a/hw/nseries.c b/hw/nseries.c index b8c6a29..b199cb9 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -37,7 +37,7 @@ =20 /* Nokia N8x0 support */ struct n800_s { - struct omap_mpu_state_s *cpu; + struct omap_mpu_state_s *mpu; =20 struct rfbi_chip_s blizzard; struct { @@ -135,10 +135,10 @@ static void n800_mmc_cs_cb(void *opaque, int line, = int level) =20 static void n8x0_gpio_setup(struct n800_s *s) { - qemu_irq *mmc_cs =3D qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc,= 1); - qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]); + qemu_irq *mmc_cs =3D qemu_allocate_irqs(n800_mmc_cs_cb, s->mpu->mmc,= 1); + qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]); =20 - qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO)); + qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO)); } =20 #define MAEMO_CAL_HEADER(...) \ @@ -179,8 +179,8 @@ static void n8x0_nand_setup(struct n800_s *s) } qdev_init_nofail(s->nand); sysbus_connect_irq(sysbus_from_qdev(s->nand), 0, - qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO)= ); - omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, + qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO)= ); + omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS, sysbus_mmio_get_region(sysbus_from_qdev(s->nand), 0= )); otp_region =3D onenand_raw_otp(s->nand); =20 @@ -192,13 +192,13 @@ static void n8x0_nand_setup(struct n800_s *s) static void n8x0_i2c_setup(struct n800_s *s) { DeviceState *dev; - qemu_irq tmp_irq =3D qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO= ); - i2c_bus *i2c =3D omap_i2c_bus(s->cpu->i2c[0]); + qemu_irq tmp_irq =3D qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO= ); + i2c_bus *i2c =3D omap_i2c_bus(s->mpu->i2c[0]); =20 /* Attach a menelaus PM chip */ dev =3D i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR); qdev_connect_gpio_out(dev, 3, - qdev_get_gpio_in(s->cpu->ih[0], + qdev_get_gpio_in(s->mpu->ih[0], OMAP_INT_24XX_SYS_NIRQ)); =20 qemu_system_powerdown =3D qdev_get_gpio_in(dev, 3); @@ -263,8 +263,8 @@ static void n800_tsc_kbd_setup(struct n800_s *s) /* XXX: are the three pins inverted inside the chip between the * tsc and the cpu (N4111)? */ qemu_irq penirq =3D NULL; /* NC */ - qemu_irq kbirq =3D qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GP= IO); - qemu_irq dav =3D qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO); + qemu_irq kbirq =3D qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GP= IO); + qemu_irq dav =3D qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO); =20 s->ts.chip =3D tsc2301_init(penirq, kbirq, dav); s->ts.opaque =3D s->ts.chip->opaque; @@ -283,7 +283,7 @@ static void n800_tsc_kbd_setup(struct n800_s *s) =20 static void n810_tsc_setup(struct n800_s *s) { - qemu_irq pintdav =3D qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO= ); + qemu_irq pintdav =3D qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO= ); =20 s->ts.opaque =3D tsc2005_init(pintdav); s->ts.txrx =3D tsc2005_txrx; @@ -375,7 +375,7 @@ static int n810_keys[0x80] =3D { =20 static void n810_kbd_setup(struct n800_s *s) { - qemu_irq kbd_irq =3D qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GP= IO); + qemu_irq kbd_irq =3D qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GP= IO); int i; =20 for (i =3D 0; i < 0x80; i ++) @@ -388,7 +388,7 @@ static void n810_kbd_setup(struct n800_s *s) =20 /* Attach the LM8322 keyboard to the I2C bus, * should happen in n8x0_i2c_setup and s->kbd be initialised here. = */ - s->kbd =3D i2c_create_slave(omap_i2c_bus(s->cpu->i2c[0]), + s->kbd =3D i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]), "lm8323", N810_LM8323_ADDR); qdev_connect_gpio_out(s->kbd, 0, kbd_irq); } @@ -679,8 +679,8 @@ static void n8x0_spi_setup(struct n800_s *s) void *tsc =3D s->ts.opaque; void *mipid =3D mipid_init(); =20 - omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0); - omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1); + omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0); + omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1); } =20 /* This task is normally performed by the bootloader. If we're loading @@ -735,20 +735,20 @@ static void n8x0_dss_setup(struct n800_s *s) s->blizzard.write =3D s1d13745_write; s->blizzard.read =3D s1d13745_read; =20 - omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard); + omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard); } =20 static void n8x0_cbus_setup(struct n800_s *s) { - qemu_irq dat_out =3D qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GP= IO); - qemu_irq retu_irq =3D qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO)= ; - qemu_irq tahvo_irq =3D qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPI= O); + qemu_irq dat_out =3D qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GP= IO); + qemu_irq retu_irq =3D qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO)= ; + qemu_irq tahvo_irq =3D qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPI= O); =20 CBus *cbus =3D cbus_init(dat_out); =20 - qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk); - qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat); - qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel); + qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk); + qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat); + qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel); =20 cbus_attach(cbus, s->retu =3D retu_init(retu_irq, 1)); cbus_attach(cbus, s->tahvo =3D tahvo_init(tahvo_irq, 1)); @@ -757,14 +757,14 @@ static void n8x0_cbus_setup(struct n800_s *s) static void n8x0_uart_setup(struct n800_s *s) { CharDriverState *radio =3D uart_hci_init( - qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPI= O)); + qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPI= O)); =20 - qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO, + qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO, csrhci_pins_get(radio)[csrhci_pin_reset]); - qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO, + qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO, csrhci_pins_get(radio)[csrhci_pin_wakeup]); =20 - omap_uart_attach(s->cpu->uart[BT_UART], radio); + omap_uart_attach(s->mpu->uart[BT_UART], radio); } =20 static void n8x0_usb_setup(struct n800_s *s) @@ -774,13 +774,13 @@ static void n8x0_usb_setup(struct n800_s *s) dev =3D sysbus_from_qdev(s->usb); qdev_init_nofail(s->usb); sysbus_connect_irq(dev, 0, - qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO= )); + qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO= )); /* Using the NOR interface */ - omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS, + omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS, sysbus_mmio_get_region(dev, 0)); - omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS, + omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS, sysbus_mmio_get_region(dev, 1)); - qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO, + qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO, qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */ } =20 @@ -1023,11 +1023,11 @@ static void n8x0_boot_init(void *opaque) n800_dss_init(&s->blizzard); =20 /* CPU setup */ - s->cpu->cpu->env.GE =3D 0x5; + s->mpu->cpu->env.GE =3D 0x5; =20 /* If the machine has a slided keyboard, open it */ if (s->kbd) - qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO)); + qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO)); } =20 #define OMAP_TAG_NOKIA_BT 0x4e01 @@ -1281,7 +1281,7 @@ static void n8x0_init(ram_addr_t ram_size, const ch= ar *boot_device, int sdram_size =3D binfo->ram_size; DisplayState *ds; =20 - s->cpu =3D omap2420_mpu_init(sysmem, sdram_size, cpu_model); + s->mpu =3D omap2420_mpu_init(sysmem, sdram_size, cpu_model); =20 /* Setup peripherals * @@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const ch= ar *boot_device, binfo->kernel_filename =3D kernel_filename; binfo->kernel_cmdline =3D kernel_cmdline; binfo->initrd_filename =3D initrd_filename; - arm_load_kernel(&s->cpu->cpu->env, binfo); + arm_load_kernel(&s->mpu->cpu->env, binfo); =20 qemu_register_reset(n8x0_boot_init, s); } @@ -1338,7 +1338,7 @@ static void n8x0_init(ram_addr_t ram_size, const ch= ar *boot_device, int rom_size; uint8_t nolo_tags[0x10000]; /* No, wait, better start at the ROM. */ - s->cpu->cpu->env.regs[15] =3D OMAP2_Q2_BASE + 0x400000; + s->mpu->cpu->env.regs[15] =3D OMAP2_Q2_BASE + 0x400000; =20 /* This is intended for loading the `secondary.bin' program from * Nokia images (the NOLO bootloader). The entry point seems --=20 1.7.7