From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33964) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0vG-0004Vr-Le for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SU0vD-00038n-Qk for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:10 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:34238) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0vD-00030M-IP for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:07 -0400 From: Peter Maydell Date: Mon, 14 May 2012 20:02:59 +0100 Message-Id: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH qom-next v2 00/33] target-arm: refactor copro register implementation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rusty Russell , Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org This patchseries refactors the target-arm handling of coprocessor registers so that you define each register with a struct (and possibly some read/write/reset functions), rather than having huge nested switch statements in get_cp15()/set_cp15(). My main aim here was to get rid of the unmaintainable switch statements. The series also removes all the "behaviour depends on value of main ID register" code by a combination of defining implementation-specific cp15 regs in the implementation subclass instance init functions, and some extra feature bits. As well as get/set_cp15, we also can remove the rather limited existing effort at "define a cp register" used by the pxa2xx boards, and the framework has 64 bit register support which should provide a nice clean base to implement LPAE registers. Patch 1 is a preliminary bugfix to avoid a problem exposed by later patches in the series. Patch 2 (was patch 1 in v1) defines all the new infrastructure/framework, while leaving the old functions in place. The remaining patches convert small subsets of the cp registers, until everything has moved over and the old functions can be deleted. The conversion functions mostly take the approach of preserving the old QEMU behaviour even if it's not really right. However in some cases I have tightened up behaviour where it was both obviously wrong and painful to reproduce the same brokenness in the new scheme. I've generally remarked on those cases in the individual commit comments. I've rebased v2 to sit on top of qom-next. I don't think it requires anything from there but it will avoid some conflicts because of changes in there to the pxa2xx files. Changes since v1: * rebase on qom-next * cptype_valid(), cp_access_ok() return type changed to bool * dropped unused fn encoded_cp_matches_type() * added an ARM_CP_OVERRIDE flag which has to be used for one cp definition to override another: this is just to avoid overriding happening by accident * make cp_reg_reset prototype use gpointer, name 3rd argument "opaque" * switch to ARMCPU* not CPUARMState* in most APIs (but not in the CPRead/CPWrite/CPReset callbacks) * add an instance_finalize to ARMCPU so we can destroy the hashtable (avoids leaking a hashtable on every thread deletion in linux-user mode) * 1176 should have ARM_FEATURE_CACHE_BLOCK_OPS * added a patch at start of series which fixes the 11mpcore cache type register. Otherwise Linux thinks the core has an aliasing VIPT cache and tries to use the cache block ops, and we would fail to boot when the 64 bit block ops are restricted to only the cores which should actually have them. Peter Maydell (33): target-arm: Fix 11MPCore cache type register value target-arm: initial coprocessor register framework hw/pxa2xx: Convert cp14 perf registers to new scheme hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs hw/pxa2xx_pic: Convert coprocessor registers to new scheme target-arm: Remove old cpu_arm_set_cp_io infrastructure target-arm: Add register_cp_regs_for_features() target-arm: Convert debug registers to cp_reginfo target-arm: Convert TEECR, TEEHBR to new scheme target-arm: Convert WFI/barriers special cases to cp_reginfo target-arm: Convert TLS registers target-arm: Convert performance monitor registers target-arm: Convert generic timer cp15 regs target-arm: Convert cp15 c3 register target-arm: Convert MMU fault status cp15 registers target-arm: Convert cp15 crn=2 registers target-arm: Convert cp15 crn=13 registers target-arm: Convert cp15 crn=10 registers target-arm: Convert cp15 crn=15 registers target-arm: Convert cp15 MMU TLB control target-arm: Convert cp15 VA-PA translation registers target-arm: convert cp15 crn=7 registers target-arm: Convert cp15 crn=6 registers target-arm: Convert cp15 crn=9 registers target-arm: Convert cp15 crn=1 registers target-arm: Convert cp15 crn=0 crm={1,2} feature registers target-arm: Convert cp15 cache ID registers target-arm: Convert MPIDR target-arm: Convert final ID registers target-arm: Remove c0_cachetype CPUARMState field target-arm: Move block cache ops to new cp15 framework target-arm: Remove remaining old cp15 infrastructure target-arm: Remove ARM_CPUID_* macros hw/pxa2xx.c | 285 +++---- hw/pxa2xx_pic.c | 53 +- linux-user/cpu-uname.c | 5 +- target-arm/cpu-qom.h | 5 + target-arm/cpu.c | 230 +++++-- target-arm/cpu.h | 248 +++++- target-arm/helper.c | 2070 +++++++++++++++++++++++++++--------------------- target-arm/helper.h | 11 +- target-arm/machine.c | 2 - target-arm/op_helper.c | 42 +- target-arm/translate.c | 474 ++++-------- 11 files changed, 1889 insertions(+), 1536 deletions(-)