From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33840) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0v7-00044y-10 for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SU0v4-00036G-Ag for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:00 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:34238) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0v4-00030M-32 for qemu-devel@nongnu.org; Mon, 14 May 2012 15:26:58 -0400 From: Peter Maydell Date: Mon, 14 May 2012 20:03:13 +0100 Message-Id: <1337022212-22219-15-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH qom-next v2 14/33] target-arm: Convert cp15 c3 register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rusty Russell , Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: Peter Maydell --- target-arm/helper.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index a92bbc7..0f94c2f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -61,6 +61,13 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + env->cp15.c3 = value; + tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ + return 0; +} + static const ARMCPRegInfo cp_reginfo[] = { /* DBGDIDR: just RAZ. In particular this means the "debug architecture * version" bits will read as a reserved value, which should cause @@ -68,6 +75,11 @@ static const ARMCPRegInfo cp_reginfo[] = { */ { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* MMU Domain access control / MPU write buffer control */ + { .name = "DACR", .cp = 15, + .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), + .resetvalue = 0, .writefn = dacr_write }, REGINFO_SENTINEL }; @@ -1556,10 +1568,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) } } break; - case 3: /* MMU Domain access control / MPU write buffer control. */ - env->cp15.c3 = val; - tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ - break; case 4: /* Reserved. */ goto bad_reg; case 5: /* MMU Fault status / MPU access permission. */ @@ -1947,8 +1955,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) goto bad_reg; } } - case 3: /* MMU Domain access control / MPU write buffer control. */ - return env->cp15.c3; case 4: /* Reserved. */ goto bad_reg; case 5: /* MMU Fault status / MPU access permission. */ -- 1.7.1