From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33626) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0uo-0003AI-Tf for qemu-devel@nongnu.org; Mon, 14 May 2012 15:26:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SU0un-00031a-1H for qemu-devel@nongnu.org; Mon, 14 May 2012 15:26:42 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:34238) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0um-00030M-PM for qemu-devel@nongnu.org; Mon, 14 May 2012 15:26:40 -0400 From: Peter Maydell Date: Mon, 14 May 2012 20:03:30 +0100 Message-Id: <1337022212-22219-32-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH qom-next v2 31/33] target-arm: Move block cache ops to new cp15 framework List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rusty Russell , Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell --- target-arm/helper.c | 13 +++++++++++++ target-arm/translate.c | 7 +------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 753ab5c..805ca98 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -815,6 +815,19 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { /* We never have a a block transfer operation in progress */ { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* The cache ops themselves: these all NOP for QEMU */ + { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, REGINFO_SENTINEL }; diff --git a/target-arm/translate.c b/target-arm/translate.c index f4e9435..fcdc9d3 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2451,12 +2451,7 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; if ((insn & (1 << 25)) == 0) { - if (insn & (1 << 20)) { - /* mrrc */ - return 1; - } - /* mcrr. Used for block cache operations, so implement as no-op. */ - return 0; + return 1; } if ((insn & (1 << 4)) == 0) { /* cdp */ -- 1.7.1