From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Rusty Russell" <rusty.russell@linaro.org>,
"Paul Brook" <paul@codesourcery.com>,
"Andreas Färber" <afaerber@suse.de>,
patches@linaro.org
Subject: [Qemu-devel] [PATCH qom-next v2 33/33] target-arm: Remove ARM_CPUID_* macros
Date: Mon, 14 May 2012 20:03:32 +0100 [thread overview]
Message-ID: <1337022212-22219-34-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org>
All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/cpu-uname.c | 5 +---
target-arm/cpu.c | 50 ++++++++++++++++++++++++------------------------
target-arm/cpu.h | 27 -------------------------
3 files changed, 26 insertions(+), 56 deletions(-)
diff --git a/linux-user/cpu-uname.c b/linux-user/cpu-uname.c
index ddc37be..59cd647 100644
--- a/linux-user/cpu-uname.c
+++ b/linux-user/cpu-uname.c
@@ -35,10 +35,7 @@ const char *cpu_to_uname_machine(void *cpu_env)
* armv7l; to get a list of CPU arch names from the linux source, use:
* grep arch_name: -A1 linux/arch/arm/mm/proc-*.S
* see arch/arm/kernel/setup.c: setup_processor()
- *
- * to test by CPU id, compare cpu_env->cp15.c0_cpuid to ARM_CPUID_*
- * defines and to test by CPU feature, use arm_feature(cpu_env,
- * ARM_FEATURE_*) */
+ */
/* in theory, endianness is configurable on some ARM CPUs, but this isn't
* used in user mode emulation */
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 3ea3527..ae57953 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -205,7 +205,7 @@ static void arm926_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
- cpu->midr = ARM_CPUID_ARM926;
+ cpu->midr = 0x41069265;
cpu->reset_fpsid = 0x41011090;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00090078;
@@ -217,7 +217,7 @@ static void arm946_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_MPU);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = ARM_CPUID_ARM946;
+ cpu->midr = 0x41059461;
cpu->ctr = 0x0f004006;
cpu->reset_sctlr = 0x00000078;
}
@@ -230,7 +230,7 @@ static void arm1026_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
- cpu->midr = ARM_CPUID_ARM1026;
+ cpu->midr = 0x4106a262;
cpu->reset_fpsid = 0x410110a0;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00090078;
@@ -262,7 +262,7 @@ static void arm1136_r2_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- cpu->midr = ARM_CPUID_ARM1136_R2;
+ cpu->midr = 0x4107b362;
cpu->reset_fpsid = 0x410120b4;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
@@ -292,7 +292,7 @@ static void arm1136_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- cpu->midr = ARM_CPUID_ARM1136;
+ cpu->midr = 0x4117b363;
cpu->reset_fpsid = 0x410120b4;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
@@ -322,7 +322,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
- cpu->midr = ARM_CPUID_ARM1176;
+ cpu->midr = 0x410fb767;
cpu->reset_fpsid = 0x410120b5;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
@@ -351,7 +351,7 @@ static void arm11mpcore_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VAPA);
set_feature(&cpu->env, ARM_FEATURE_MPIDR);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = ARM_CPUID_ARM11MPCORE;
+ cpu->midr = 0x410fb022;
cpu->reset_fpsid = 0x410120b4;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
@@ -376,7 +376,7 @@ static void cortex_m3_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
- cpu->midr = ARM_CPUID_CORTEXM3;
+ cpu->midr = 0x410fc231;
}
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
@@ -395,7 +395,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = ARM_CPUID_CORTEXA8;
+ cpu->midr = 0x410fc080;
cpu->reset_fpsid = 0x410330c0;
cpu->mvfr0 = 0x11110222;
cpu->mvfr1 = 0x00011100;
@@ -464,7 +464,7 @@ static void cortex_a9_initfn(Object *obj)
* and valid configurations; we don't model A9UP).
*/
set_feature(&cpu->env, ARM_FEATURE_V7MP);
- cpu->midr = ARM_CPUID_CORTEXA9;
+ cpu->midr = 0x410fc090;
cpu->reset_fpsid = 0x41033090;
cpu->mvfr0 = 0x11110222;
cpu->mvfr1 = 0x01111111;
@@ -532,7 +532,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = ARM_CPUID_CORTEXA15;
+ cpu->midr = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;
cpu->mvfr0 = 0x10110222;
cpu->mvfr1 = 0x11111111;
@@ -573,7 +573,7 @@ static void sa1100_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = ARM_CPUID_SA1100;
+ cpu->midr = 0x4401A11B;
cpu->reset_sctlr = 0x00000070;
}
@@ -582,7 +582,7 @@ static void sa1110_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- cpu->midr = ARM_CPUID_SA1110;
+ cpu->midr = 0x6901B119;
cpu->reset_sctlr = 0x00000070;
}
@@ -591,7 +591,7 @@ static void pxa250_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = ARM_CPUID_PXA250;
+ cpu->midr = 0x69052100;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -601,7 +601,7 @@ static void pxa255_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = ARM_CPUID_PXA255;
+ cpu->midr = 0x69052d00;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -611,7 +611,7 @@ static void pxa260_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = ARM_CPUID_PXA260;
+ cpu->midr = 0x69052903;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -621,7 +621,7 @@ static void pxa261_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = ARM_CPUID_PXA261;
+ cpu->midr = 0x69052d05;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -631,7 +631,7 @@ static void pxa262_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
- cpu->midr = ARM_CPUID_PXA262;
+ cpu->midr = 0x69052d06;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -642,7 +642,7 @@ static void pxa270a0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = ARM_CPUID_PXA270_A0;
+ cpu->midr = 0x69054110;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -653,7 +653,7 @@ static void pxa270a1_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = ARM_CPUID_PXA270_A1;
+ cpu->midr = 0x69054111;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -664,7 +664,7 @@ static void pxa270b0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = ARM_CPUID_PXA270_B0;
+ cpu->midr = 0x69054112;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -675,7 +675,7 @@ static void pxa270b1_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = ARM_CPUID_PXA270_B1;
+ cpu->midr = 0x69054113;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -686,7 +686,7 @@ static void pxa270c0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = ARM_CPUID_PXA270_C0;
+ cpu->midr = 0x69054114;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -697,7 +697,7 @@ static void pxa270c5_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
- cpu->midr = ARM_CPUID_PXA270_C5;
+ cpu->midr = 0x69054117;
cpu->ctr = 0xd172172;
cpu->reset_sctlr = 0x00000078;
}
@@ -712,7 +712,7 @@ static void arm_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
- cpu->midr = ARM_CPUID_ANY;
+ cpu->midr = 0xffffffff;
}
typedef struct ARMCPUInfo {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 27e398b..33afa18 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -606,36 +606,9 @@ static inline bool cp_access_ok(CPUARMState *env,
conventional cores (ie. Application or Realtime profile). */
#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
-#define ARM_CPUID(env) (env->cp15.c0_cpuid)
-#define ARM_CPUID_ARM1026 0x4106a262
-#define ARM_CPUID_ARM926 0x41069265
-#define ARM_CPUID_ARM946 0x41059461
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#define ARM_CPUID_SA1100 0x4401A11B
-#define ARM_CPUID_SA1110 0x6901B119
-#define ARM_CPUID_PXA250 0x69052100
-#define ARM_CPUID_PXA255 0x69052d00
-#define ARM_CPUID_PXA260 0x69052903
-#define ARM_CPUID_PXA261 0x69052d05
-#define ARM_CPUID_PXA262 0x69052d06
-#define ARM_CPUID_PXA270 0x69054110
-#define ARM_CPUID_PXA270_A0 0x69054110
-#define ARM_CPUID_PXA270_A1 0x69054111
-#define ARM_CPUID_PXA270_B0 0x69054112
-#define ARM_CPUID_PXA270_B1 0x69054113
-#define ARM_CPUID_PXA270_C0 0x69054114
-#define ARM_CPUID_PXA270_C5 0x69054117
-#define ARM_CPUID_ARM1136 0x4117b363
-#define ARM_CPUID_ARM1136_R2 0x4107b362
-#define ARM_CPUID_ARM1176 0x410fb767
-#define ARM_CPUID_ARM11MPCORE 0x410fb022
-#define ARM_CPUID_CORTEXA8 0x410fc080
-#define ARM_CPUID_CORTEXA9 0x410fc090
-#define ARM_CPUID_CORTEXA15 0x412fc0f1
-#define ARM_CPUID_CORTEXM3 0x410fc231
-#define ARM_CPUID_ANY 0xffffffff
#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
--
1.7.1
next prev parent reply other threads:[~2012-05-14 19:26 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-14 19:02 [Qemu-devel] [PATCH qom-next v2 00/33] target-arm: refactor copro register implementation Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 01/33] target-arm: Fix 11MPCore cache type register value Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 02/33] target-arm: initial coprocessor register framework Peter Maydell
2012-05-18 14:46 ` Andreas Färber
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 03/33] hw/pxa2xx: Convert cp14 perf registers to new scheme Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 04/33] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 05/33] hw/pxa2xx_pic: Convert coprocessor registers to new scheme Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 06/33] target-arm: Remove old cpu_arm_set_cp_io infrastructure Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 07/33] target-arm: Add register_cp_regs_for_features() Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 08/33] target-arm: Convert debug registers to cp_reginfo Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 09/33] target-arm: Convert TEECR, TEEHBR to new scheme Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 10/33] target-arm: Convert WFI/barriers special cases to cp_reginfo Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 11/33] target-arm: Convert TLS registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 12/33] target-arm: Convert performance monitor registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 13/33] target-arm: Convert generic timer cp15 regs Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 14/33] target-arm: Convert cp15 c3 register Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 15/33] target-arm: Convert MMU fault status cp15 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 16/33] target-arm: Convert cp15 crn=2 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 17/33] target-arm: Convert cp15 crn=13 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 18/33] target-arm: Convert cp15 crn=10 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 19/33] target-arm: Convert cp15 crn=15 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 20/33] target-arm: Convert cp15 MMU TLB control Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 21/33] target-arm: Convert cp15 VA-PA translation registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 22/33] target-arm: convert cp15 crn=7 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 23/33] target-arm: Convert cp15 crn=6 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 24/33] target-arm: Convert cp15 crn=9 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 25/33] target-arm: Convert cp15 crn=1 registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 26/33] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 27/33] target-arm: Convert cp15 cache ID registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 28/33] target-arm: Convert MPIDR Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 29/33] target-arm: Convert final ID registers Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 30/33] target-arm: Remove c0_cachetype CPUARMState field Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 31/33] target-arm: Move block cache ops to new cp15 framework Peter Maydell
2012-05-14 19:03 ` [Qemu-devel] [PATCH qom-next v2 32/33] target-arm: Remove remaining old cp15 infrastructure Peter Maydell
2012-05-14 19:03 ` Peter Maydell [this message]
2012-06-19 17:06 ` [Qemu-devel] [PATCH qom-next v2 33/33] target-arm: Remove ARM_CPUID_* macros Andreas Färber
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