From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:33961) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0vG-0004Vq-EV for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SU0vE-00038x-NC for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:10 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:34238) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SU0vE-00030M-Dh for qemu-devel@nongnu.org; Mon, 14 May 2012 15:27:08 -0400 From: Peter Maydell Date: Mon, 14 May 2012 20:03:06 +0100 Message-Id: <1337022212-22219-8-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH qom-next v2 07/33] target-arm: Add register_cp_regs_for_features() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rusty Russell , Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , patches@linaro.org Add new function register_cp_regs_for_features() as a place to register coprocessor registers dependent on feature flags. Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 2 ++ target-arm/helper.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 848ac2f..4ccfc89 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -107,5 +107,6 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) void arm_cpu_realize(ARMCPU *cpu); +void register_cp_regs_for_features(ARMCPU *cpu); #endif diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 6456a3d..1aff266 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -216,6 +216,8 @@ void arm_cpu_realize(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_VFP3)) { set_feature(env, ARM_FEATURE_VFP); } + + register_cp_regs_for_features(cpu); } /* CPU models */ diff --git a/target-arm/helper.c b/target-arm/helper.c index dbb3c04..c002050 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -61,6 +61,17 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +void register_cp_regs_for_features(ARMCPU *cpu) +{ + /* Register all the coprocessor registers based on feature bits */ + CPUARMState *env = &cpu->env; + if (arm_feature(env, ARM_FEATURE_M)) { + /* M profile has no coprocessor registers */ + return; + } + +} + ARMCPU *cpu_arm_init(const char *cpu_model) { ARMCPU *cpu; -- 1.7.1