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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Thu, 17 May 2012 10:24:53 +1000
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Subject: Re: [Qemu-devel] [PATCH 13/13] iommu: Add a memory barrier to DMA
 RW function
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To: Anthony Liguori <anthony@codemonkey.ws>
Cc: "Michael S. Tsirkin" <mst@redhat.com>, qemu-devel@nongnu.org, David Gibson <david@gibson.dropbear.id.au>

On Thu, 2012-05-17 at 10:07 +1000, Benjamin Herrenschmidt wrote:

 .../...

> Also, should I make the barrier conditional to kvm_enabled() ? IE. It's
> pointless in full emulation and might actually be a performance hit on
> something already quite slow...

Finally ... something like smp_mb() in qemu will turn into a lock op or
an mfence on x86, ie not a nop.

That means overhead from today's implementation, which leads to the
question ... is today implementation correct ? IE. Is a barrier needed
on x86 as well or not ?

If not (I'm trying to figure out why exactly does x86 have a barrier in
the first place and when it's in order), then I might add a new barrier
type in qemu-barriers.h, something like dma_mb(), and define it as a nop
on x86, a lwsync or sync (still thinking about it) on ppc, and
__sync_synchronize() on unknown archs.

Any x86 guru around cares to explain me what exactly is the x86 memory
model and when does it need barriers ?

Cheers,
Ben.