From: Jia Liu <proljc@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 00/15] Qemu Openrisc support
Date: Thu, 17 May 2012 16:35:43 +0800 [thread overview]
Message-ID: <1337243758-11802-1-git-send-email-proljc@gmail.com> (raw)
This is the Opencores Openrisc 1200 support for Qemu.
Full implementation of the system-model and linux-user-model support.
Openrisc 1200 is a Opencores Open Source CPU,
its Architecture Manual can be find at
http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf
Signed-off-by: Jia Liu <proljc@gmail.com>
---
Version History:
V1:
- add Qemu Openrisc support.
- well tested on x64 machine, and final tested x86 machine.
Jia Liu (15):
Openrisc: add target stub
Openrisc: add MMU support
Openrisc: add instructions translation
Openrisc: add interrupt support
Openrisc: add exception support
Openrisc: add int instruction helpers
Openrisc: add float instruction helpers
Openrisc: add programmable interrupt controller support
Openrisc: add timer support
Openrisc: add a simulation board
Openrisc: add system instruction helpers
Openrisc: add gdb stub support
Openrisc: add linux syscall, signal and termbits
Openrisc: add linux user support
Openrisc: add testcases
Makefile.target | 7 +
arch_init.c | 2 +
arch_init.h | 1 +
configure | 9 +-
cpu-exec.c | 19 +
default-configs/or32-linux-user.mak | 2 +
default-configs/or32-softmmu.mak | 6 +
elf.h | 2 +
gdbstub.c | 64 ++
hw/openrisc_cpudev.h | 30 +
hw/openrisc_pic.c | 79 ++
hw/openrisc_sim.c | 140 ++++
hw/openrisc_timer.c | 153 ++++
linux-user/elfload.c | 41 +
linux-user/main.c | 100 +++
linux-user/openrisc/syscall.h | 24 +
linux-user/openrisc/syscall_nr.h | 506 ++++++++++++
linux-user/openrisc/target_signal.h | 26 +
linux-user/openrisc/termbits.h | 294 +++++++
linux-user/signal.c | 229 ++++++
linux-user/syscall.c | 2 +-
linux-user/syscall_defs.h | 40 +-
poison.h | 1 +
target-openrisc/cpu-qom.h | 70 ++
target-openrisc/cpu.c | 74 ++
target-openrisc/cpu.h | 299 +++++++
target-openrisc/excp.c | 27 +
target-openrisc/excp.h | 28 +
target-openrisc/excp_helper.c | 28 +
target-openrisc/fpu_helper.c | 93 +++
target-openrisc/helper.c | 109 +++
target-openrisc/helper.h | 46 ++
target-openrisc/int_helper.c | 126 +++
target-openrisc/intrp_helper.c | 53 ++
target-openrisc/machine.c | 76 ++
target-openrisc/mem.c | 261 ++++++
target-openrisc/mem_helper.c | 71 ++
target-openrisc/sys_helper.c | 227 ++++++
target-openrisc/translate.c | 1484 +++++++++++++++++++++++++++++++++++
tests/tcg/openrisc/Makefile | 73 ++
tests/tcg/openrisc/test_add.c | 34 +
tests/tcg/openrisc/test_addc.c | 37 +
tests/tcg/openrisc/test_addi.c | 31 +
tests/tcg/openrisc/test_addic.c | 32 +
tests/tcg/openrisc/test_and_or.c | 61 ++
tests/tcg/openrisc/test_bf.c | 46 ++
tests/tcg/openrisc/test_bnf.c | 50 ++
tests/tcg/openrisc/test_div.c | 32 +
tests/tcg/openrisc/test_extx.c | 71 ++
tests/tcg/openrisc/test_fx.c | 53 ++
tests/tcg/openrisc/test_j.c | 26 +
tests/tcg/openrisc/test_jal.c | 26 +
tests/tcg/openrisc/test_lf_add.c | 32 +
tests/tcg/openrisc/test_lf_div.c | 33 +
tests/tcg/openrisc/test_lf_eqd.c | 44 ++
tests/tcg/openrisc/test_lf_eqs.c | 43 +
tests/tcg/openrisc/test_lf_ged.c | 45 ++
tests/tcg/openrisc/test_lf_ges.c | 45 ++
tests/tcg/openrisc/test_lf_gtd.c | 45 ++
tests/tcg/openrisc/test_lf_gts.c | 45 ++
tests/tcg/openrisc/test_lf_led.c | 43 +
tests/tcg/openrisc/test_lf_les.c | 45 ++
tests/tcg/openrisc/test_lf_ltd.c | 45 ++
tests/tcg/openrisc/test_lf_lts.c | 45 ++
tests/tcg/openrisc/test_lf_mul.c | 22 +
tests/tcg/openrisc/test_lf_ned.c | 46 ++
tests/tcg/openrisc/test_lf_nes.c | 46 ++
tests/tcg/openrisc/test_lf_rem.c | 31 +
tests/tcg/openrisc/test_lf_sub.c | 31 +
tests/tcg/openrisc/test_logic.c | 100 +++
tests/tcg/openrisc/test_lx.c | 78 ++
tests/tcg/openrisc/test_movhi.c | 30 +
tests/tcg/openrisc/test_mul.c | 47 ++
tests/tcg/openrisc/test_sfeq.c | 43 +
tests/tcg/openrisc/test_sfeqi.c | 39 +
tests/tcg/openrisc/test_sfges.c | 44 ++
tests/tcg/openrisc/test_sfgesi.c | 40 +
tests/tcg/openrisc/test_sfgeu.c | 44 ++
tests/tcg/openrisc/test_sfgeui.c | 41 +
tests/tcg/openrisc/test_sfgts.c | 45 ++
tests/tcg/openrisc/test_sfgtsi.c | 41 +
tests/tcg/openrisc/test_sfgtu.c | 43 +
tests/tcg/openrisc/test_sfgtui.c | 42 +
tests/tcg/openrisc/test_sfles.c | 26 +
tests/tcg/openrisc/test_sflesi.c | 39 +
tests/tcg/openrisc/test_sfleu.c | 43 +
tests/tcg/openrisc/test_sfleui.c | 39 +
tests/tcg/openrisc/test_sflts.c | 43 +
tests/tcg/openrisc/test_sfltsi.c | 38 +
tests/tcg/openrisc/test_sfltu.c | 41 +
tests/tcg/openrisc/test_sfltui.c | 39 +
tests/tcg/openrisc/test_sfne.c | 43 +
tests/tcg/openrisc/test_sfnei.c | 38 +
93 files changed, 7168 insertions(+), 5 deletions(-)
create mode 100644 default-configs/or32-linux-user.mak
create mode 100644 default-configs/or32-softmmu.mak
create mode 100644 hw/openrisc_cpudev.h
create mode 100644 hw/openrisc_pic.c
create mode 100644 hw/openrisc_sim.c
create mode 100644 hw/openrisc_timer.c
create mode 100644 linux-user/openrisc/syscall.h
create mode 100644 linux-user/openrisc/syscall_nr.h
create mode 100644 linux-user/openrisc/target_signal.h
create mode 100644 linux-user/openrisc/termbits.h
create mode 100644 target-openrisc/cpu-qom.h
create mode 100644 target-openrisc/cpu.c
create mode 100644 target-openrisc/cpu.h
create mode 100644 target-openrisc/excp.c
create mode 100644 target-openrisc/excp.h
create mode 100644 target-openrisc/excp_helper.c
create mode 100644 target-openrisc/fpu_helper.c
create mode 100644 target-openrisc/helper.c
create mode 100644 target-openrisc/helper.h
create mode 100644 target-openrisc/int_helper.c
create mode 100644 target-openrisc/intrp_helper.c
create mode 100644 target-openrisc/machine.c
create mode 100644 target-openrisc/mem.c
create mode 100644 target-openrisc/mem_helper.c
create mode 100644 target-openrisc/sys_helper.c
create mode 100644 target-openrisc/translate.c
create mode 100644 tests/tcg/openrisc/Makefile
create mode 100644 tests/tcg/openrisc/test_add.c
create mode 100644 tests/tcg/openrisc/test_addc.c
create mode 100644 tests/tcg/openrisc/test_addi.c
create mode 100644 tests/tcg/openrisc/test_addic.c
create mode 100644 tests/tcg/openrisc/test_and_or.c
create mode 100644 tests/tcg/openrisc/test_bf.c
create mode 100644 tests/tcg/openrisc/test_bnf.c
create mode 100644 tests/tcg/openrisc/test_div.c
create mode 100644 tests/tcg/openrisc/test_extx.c
create mode 100644 tests/tcg/openrisc/test_fx.c
create mode 100644 tests/tcg/openrisc/test_j.c
create mode 100644 tests/tcg/openrisc/test_jal.c
create mode 100644 tests/tcg/openrisc/test_lf_add.c
create mode 100644 tests/tcg/openrisc/test_lf_div.c
create mode 100644 tests/tcg/openrisc/test_lf_eqd.c
create mode 100644 tests/tcg/openrisc/test_lf_eqs.c
create mode 100644 tests/tcg/openrisc/test_lf_ged.c
create mode 100644 tests/tcg/openrisc/test_lf_ges.c
create mode 100644 tests/tcg/openrisc/test_lf_gtd.c
create mode 100644 tests/tcg/openrisc/test_lf_gts.c
create mode 100644 tests/tcg/openrisc/test_lf_led.c
create mode 100644 tests/tcg/openrisc/test_lf_les.c
create mode 100644 tests/tcg/openrisc/test_lf_ltd.c
create mode 100644 tests/tcg/openrisc/test_lf_lts.c
create mode 100644 tests/tcg/openrisc/test_lf_mul.c
create mode 100644 tests/tcg/openrisc/test_lf_ned.c
create mode 100644 tests/tcg/openrisc/test_lf_nes.c
create mode 100644 tests/tcg/openrisc/test_lf_rem.c
create mode 100644 tests/tcg/openrisc/test_lf_sub.c
create mode 100644 tests/tcg/openrisc/test_logic.c
create mode 100644 tests/tcg/openrisc/test_lx.c
create mode 100644 tests/tcg/openrisc/test_movhi.c
create mode 100644 tests/tcg/openrisc/test_mul.c
create mode 100644 tests/tcg/openrisc/test_sfeq.c
create mode 100644 tests/tcg/openrisc/test_sfeqi.c
create mode 100644 tests/tcg/openrisc/test_sfges.c
create mode 100644 tests/tcg/openrisc/test_sfgesi.c
create mode 100644 tests/tcg/openrisc/test_sfgeu.c
create mode 100644 tests/tcg/openrisc/test_sfgeui.c
create mode 100644 tests/tcg/openrisc/test_sfgts.c
create mode 100644 tests/tcg/openrisc/test_sfgtsi.c
create mode 100644 tests/tcg/openrisc/test_sfgtu.c
create mode 100644 tests/tcg/openrisc/test_sfgtui.c
create mode 100644 tests/tcg/openrisc/test_sfles.c
create mode 100644 tests/tcg/openrisc/test_sflesi.c
create mode 100644 tests/tcg/openrisc/test_sfleu.c
create mode 100644 tests/tcg/openrisc/test_sfleui.c
create mode 100644 tests/tcg/openrisc/test_sflts.c
create mode 100644 tests/tcg/openrisc/test_sfltsi.c
create mode 100644 tests/tcg/openrisc/test_sfltu.c
create mode 100644 tests/tcg/openrisc/test_sfltui.c
create mode 100644 tests/tcg/openrisc/test_sfne.c
create mode 100644 tests/tcg/openrisc/test_sfnei.c
--
1.7.9.5
next reply other threads:[~2012-05-17 8:37 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-17 8:35 Jia Liu [this message]
2012-05-17 8:35 ` [Qemu-devel] [PATCH 01/15] Openrisc: add target stub Jia Liu
2012-05-17 9:38 ` 陳韋任
2012-05-17 14:14 ` Andreas Färber
2012-05-18 1:34 ` Jia Liu
2012-05-18 2:30 ` 陳韋任
2012-05-18 2:56 ` 陳韋任
2012-05-20 14:14 ` Andreas Färber
2012-05-21 3:01 ` Jia Liu
2012-05-19 8:51 ` Blue Swirl
2012-05-20 14:11 ` Andreas Färber
2012-05-21 6:25 ` Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 02/15] Openrisc: add MMU support Jia Liu
2012-05-19 7:41 ` Blue Swirl
2012-05-21 6:24 ` Jia Liu
2012-05-21 9:03 ` 陳韋任
2012-05-21 17:41 ` Blue Swirl
2012-05-17 8:35 ` [Qemu-devel] [PATCH 03/15] Openrisc: add instructions translation Jia Liu
2012-05-17 12:11 ` Max Filippov
2012-05-18 1:04 ` Jia Liu
2012-05-18 3:53 ` 陳韋任
2012-05-18 10:33 ` Max Filippov
2012-05-19 10:02 ` Blue Swirl
2012-05-19 10:57 ` Peter Maydell
2012-05-19 11:29 ` Blue Swirl
2012-05-23 6:11 ` Jia Liu
2012-05-23 18:59 ` Blue Swirl
2012-05-25 23:50 ` Jia Liu
2012-05-26 0:37 ` Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 04/15] Openrisc: add interrupt support Jia Liu
2012-05-19 7:30 ` Blue Swirl
2012-05-23 7:06 ` Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 05/15] Openrisc: add exception support Jia Liu
2012-05-19 7:22 ` Blue Swirl
2012-05-23 7:09 ` Jia Liu
2012-05-23 19:11 ` Blue Swirl
2012-05-25 1:25 ` Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 06/15] Openrisc: add int instruction helpers Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 07/15] Openrisc: add float " Jia Liu
2012-05-19 8:29 ` Blue Swirl
2012-05-23 7:21 ` Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 08/15] Openrisc: add programmable interrupt controller support Jia Liu
2012-05-19 8:33 ` Blue Swirl
2012-05-17 8:35 ` [Qemu-devel] [PATCH 09/15] Openrisc: add timer support Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 10/15] Openrisc: add a simulation board Jia Liu
2012-05-19 7:51 ` Blue Swirl
2012-05-23 7:54 ` Jia Liu
2012-05-23 19:17 ` Blue Swirl
2012-05-25 2:31 ` Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 11/15] Openrisc: add system instruction helpers Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 12/15] Openrisc: add gdb stub support Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 13/15] Openrisc: add linux syscall, signal and termbits Jia Liu
2012-05-19 7:17 ` Blue Swirl
2012-05-19 8:57 ` Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 14/15] Openrisc: add linux user support Jia Liu
2012-05-17 8:35 ` [Qemu-devel] [PATCH 15/15] Openrisc: add testcases Jia Liu
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