From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55936) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUwE5-00066X-AL for qemu-devel@nongnu.org; Thu, 17 May 2012 04:38:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SUwDz-0003Rn-2b for qemu-devel@nongnu.org; Thu, 17 May 2012 04:38:24 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:61674) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUwDy-0002w4-QE for qemu-devel@nongnu.org; Thu, 17 May 2012 04:38:19 -0400 Received: by mail-pz0-f45.google.com with SMTP id v2so2718250dad.4 for ; Thu, 17 May 2012 01:38:17 -0700 (PDT) From: Jia Liu Date: Thu, 17 May 2012 16:35:51 +0800 Message-Id: <1337243758-11802-9-git-send-email-proljc@gmail.com> In-Reply-To: <1337243758-11802-1-git-send-email-proljc@gmail.com> References: <1337243758-11802-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH 08/15] Openrisc: add programmable interrupt controller support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org add the openrisc programmable interrupt controller support. Signed-off-by: Jia Liu --- cpu-exec.c | 17 +++++++++++++++++ hw/openrisc_pic.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/cpu-exec.c b/cpu-exec.c index ba10db1..845b2ae 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -375,6 +375,23 @@ int cpu_exec(CPUArchState *env) do_interrupt(env); next_tb = 0; } +#elif defined(TARGET_OPENRISC) + { + int idx = -1; + if ((interrupt_request & CPU_INTERRUPT_HARD) + && (env->sr & SR_IEE)) { + idx = EXCP_INT; + } + if ((interrupt_request & CPU_INTERRUPT_TIMER) + && (env->sr & SR_TEE)) { + idx = EXCP_TICK; + } + if (idx >= 0) { + env->exception_index = idx; + do_interrupt(env); + next_tb = 0; + } + } #elif defined(TARGET_SPARC) if (interrupt_request & CPU_INTERRUPT_HARD) { if (cpu_interrupts_enabled(env) && diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c index 0abdd50..52e48ec 100644 --- a/hw/openrisc_pic.c +++ b/hw/openrisc_pic.c @@ -29,3 +29,51 @@ void cpu_openrisc_pic_reset(CPUOPENRISCState *env) env->picmr = 0x00000000; env->picsr = 0x00000000; } + +/* openrisc pic handler */ +static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) +{ + CPUOPENRISCState *env = (CPUOPENRISCState *)opaque; + int i; + uint32_t irq_bit = 1 << irq; + + if (irq > 31 || irq < 0) { + return; + } + + if (level) { + env->picsr |= irq_bit; + } else { + env->picsr &= ~irq_bit; + } + + for (i = 0; i < 32; i++) { + if ((env->picsr && (1 << i)) && (env->picmr && (1 << i))) { + cpu_interrupt(env, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + env->picsr &= ~(1 << i); + } + } +} + +void cpu_openrisc_pic_init(CPUOPENRISCState *env) +{ + int i; + qemu_irq *qi; + qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, env, NR_IRQS); + + for (i = 0; i < NR_IRQS; i++) { + env->irq[i] = qi[i]; + } +} + +void cpu_openrisc_store_picmr(CPUOPENRISCState *env, uint32_t value) +{ + env->picmr |= value; +} + +void cpu_openrisc_store_picsr(CPUOPENRISCState *env, uint32_t value) +{ + env->picsr &= ~value; +} -- 1.7.9.5