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Date: Mon, 21 May 2012 07:36:08 +1000
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Subject: Re: [Qemu-devel] [PATCH 13/13] iommu: Add a memory barrier to DMA
	RW function
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To: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>, qemu-devel@nongnu.org, Anthony Liguori <anthony@codemonkey.ws>, David Gibson <david@gibson.dropbear.id.au>

On Sat, 2012-05-19 at 09:24 +0200, Paolo Bonzini wrote:

> I guess the C11/C++ guys required an isync barrier after either loads or
> stores, because they need to order the load/store vs. code accessing
> other memory.  This is not needed in QEMU because all guest accesses go
> through cpu_physical_memory_rw (or has its own barriers).

I am not sure, I don't quite see what it buys them really. I'd have to
ask Paul McKenney, he probably knows :-)

Cheers,
Ben.