From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SWrmY-0008GW-4Q for qemu-devel@nongnu.org; Tue, 22 May 2012 12:18:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SWrmP-0001fU-DB for qemu-devel@nongnu.org; Tue, 22 May 2012 12:17:57 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:34090) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SWrmP-0001ZD-4f for qemu-devel@nongnu.org; Tue, 22 May 2012 12:17:49 -0400 Received: by mail-pz0-f45.google.com with SMTP id v2so10214735dad.4 for ; Tue, 22 May 2012 09:17:48 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 22 May 2012 18:17:17 +0200 Message-Id: <1337703438-9764-7-git-send-email-pbonzini@redhat.com> In-Reply-To: <1337703438-9764-1-git-send-email-pbonzini@redhat.com> References: <1337703438-9764-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 1.2 6/7] ide: support enable/disable write cache List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kwolf@redhat.com Enabling or disabling the write cache is done with the SET FEATURES command. The command can be issued with sg_sat_set_features from sg3-utils. Signed-off-by: Paolo Bonzini --- hw/ide/core.c | 18 +++++++++++++++--- 1 files changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/ide/core.c b/hw/ide/core.c index 9785d5f..7c50567 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -1047,6 +1047,7 @@ static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) void ide_exec_cmd(IDEBus *bus, uint32_t val) { + uint16_t *identify_data; IDEState *s; int n; int lba48 = 0; @@ -1231,10 +1232,21 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val) goto abort_cmd; /* XXX: valid for CDROM ? */ switch(s->feature) { - case 0xcc: /* reverting to power-on defaults enable */ - case 0x66: /* reverting to power-on defaults disable */ case 0x02: /* write cache enable */ + bdrv_set_enable_write_cache(s->bs, true); + identify_data = (uint16_t *)s->identify_data; + put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1); + s->status = READY_STAT | SEEK_STAT; + ide_set_irq(s->bus); + break; case 0x82: /* write cache disable */ + bdrv_set_enable_write_cache(s->bs, false); + identify_data = (uint16_t *)s->identify_data; + put_le16(identify_data + 85, (1 << 14) | 1); + ide_flush_cache(s); + break; + case 0xcc: /* reverting to power-on defaults enable */ + case 0x66: /* reverting to power-on defaults disable */ case 0xaa: /* read look-ahead enable */ case 0x55: /* read look-ahead disable */ case 0x05: /* set advanced power management mode */ @@ -1250,7 +1262,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val) break; case 0x03: { /* set transfer mode */ uint8_t val = s->nsector & 0x07; - uint16_t *identify_data = (uint16_t *)s->identify_data; + identify_data = (uint16_t *)s->identify_data; switch (s->nsector >> 3) { case 0x00: /* pio default */ -- 1.7.1