From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SWsUD-00083b-3R for qemu-devel@nongnu.org; Tue, 22 May 2012 13:03:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SWsU6-0007N1-K6 for qemu-devel@nongnu.org; Tue, 22 May 2012 13:03:04 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:38834) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SWsU6-0007Km-Ce for qemu-devel@nongnu.org; Tue, 22 May 2012 13:02:58 -0400 From: Peter Maydell Date: Tue, 22 May 2012 18:02:38 +0100 Message-Id: <1337706158-3670-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH] hw/cadence_gem: Make rx_desc_addr and tx_desc_addr uint32_t List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org Make the state fields rx_desc_addr and tx_desc_addr uint32_t; this matches the VMStateDescription, and also conforms to how hardware works: the registers don't magically become larger if the device is attached to a CPU with a larger physical address size. It also fixes a compile failure if the target_phys_addr_t type is changed to 64 bits. Signed-off-by: Peter Maydell --- I'm going through fixing problems with moving target-arm to a larger physical address width so we can support the A15 Large Physical Address Extensions... hw/cadence_gem.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c index e2140ae..e563409 100644 --- a/hw/cadence_gem.c +++ b/hw/cadence_gem.c @@ -339,8 +339,8 @@ typedef struct { uint8_t phy_loop; /* Are we in phy loopback? */ /* The current DMA descriptor pointers */ - target_phys_addr_t rx_desc_addr; - target_phys_addr_t tx_desc_addr; + uint32_t rx_desc_addr; + uint32_t tx_desc_addr; } GemState; -- 1.7.1