From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SXt41-0000Cv-9H for qemu-devel@nongnu.org; Fri, 25 May 2012 07:52:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SXt3w-0005LL-8P for qemu-devel@nongnu.org; Fri, 25 May 2012 07:52:12 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43234 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SXt3w-0005L0-2b for qemu-devel@nongnu.org; Fri, 25 May 2012 07:52:08 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 25 May 2012 13:51:58 +0200 Message-Id: <1337946718-2253-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH for-1.1?] target-unicore32: Drop UC32_CPUID macros List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Guan Xuetao , =?UTF-8?q?Andreas=20F=C3=A4rber?= Any code that depends on a particular CPU type can now go through callbacks on the QOM UniCore32CPUClass. Signed-off-by: Andreas F=C3=A4rber --- target-unicore32/cpu.h | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 81c14ff..50d5695 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -120,10 +120,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_u= long val, target_ulong mask) #define UC32_HWCAP_CMOV 4 /* 1 << 2 */ #define UC32_HWCAP_UCF64 8 /* 1 << 3 */ =20 -#define UC32_CPUID(env) (env->cp0.c0_cpuid) -#define UC32_CPUID_UCV2 0x40010863 -#define UC32_CPUID_ANY 0xffffffff - #define cpu_init uc32_cpu_init #define cpu_exec uc32_cpu_exec #define cpu_signal_handler uc32_cpu_signal_handler --=20 1.7.7