From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SYW8m-0006c7-Rq for qemu-devel@nongnu.org; Sun, 27 May 2012 01:35:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SYW8l-0000Gw-1Q for qemu-devel@nongnu.org; Sun, 27 May 2012 01:35:44 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:36366) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SYW8k-0008Pv-PN for qemu-devel@nongnu.org; Sun, 27 May 2012 01:35:42 -0400 Received: by mail-pz0-f45.google.com with SMTP id v2so3249993dad.4 for ; Sat, 26 May 2012 22:35:41 -0700 (PDT) From: Jia Liu Date: Sun, 27 May 2012 13:32:52 +0800 Message-Id: <1338096779-30821-11-git-send-email-proljc@gmail.com> In-Reply-To: <1338096779-30821-1-git-send-email-proljc@gmail.com> References: <1338096779-30821-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH v2 10/17] Openrisc: add Programmable Interrupt Controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org add Programmable Interrupt Controller for openrisc. Signed-off-by: Jia Liu --- hw/openrisc_pic.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++ target-openrisc/cpu.h | 5 +++++ 2 files changed, 55 insertions(+) diff --git a/hw/openrisc_pic.c b/hw/openrisc_pic.c index 201c6bc..1c28904 100644 --- a/hw/openrisc_pic.c +++ b/hw/openrisc_pic.c @@ -25,4 +25,54 @@ /* Reset PIC */ void cpu_openrisc_pic_reset(CPUOpenriscState *env) { + env->picmr = 0x00000000; + env->picsr = 0x00000000; +} + +/* openrisc pic handler */ +static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) +{ + CPUOpenriscState *env = (CPUOpenriscState *)opaque; + int i; + uint32_t irq_bit = 1 << irq; + + if (irq > 31 || irq < 0) { + return; + } + + if (level) { + env->picsr |= irq_bit; + } else { + env->picsr &= ~irq_bit; + } + + for (i = 0; i < 32; i++) { + if ((env->picsr && (1 << i)) && (env->picmr && (1 << i))) { + cpu_interrupt(env, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + env->picsr &= ~(1 << i); + } + } +} + +void cpu_openrisc_pic_init(CPUOpenriscState *env) +{ + int i; + qemu_irq *qi; + qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, env, NR_IRQS); + + for (i = 0; i < NR_IRQS; i++) { + env->irq[i] = qi[i]; + } +} + +void cpu_openrisc_store_picmr(CPUOpenriscState *env, uint32_t value) +{ + env->picmr |= value; +} + +void cpu_openrisc_store_picsr(CPUOpenriscState *env, uint32_t value) +{ + env->picsr &= ~value; } diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 0f332ab..7417dcc 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -198,6 +198,9 @@ struct CPUOpenriscState { int (*map_address_data)(struct CPUOpenriscState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw); + + uint32_t picmr; /* Interrupt mask register */ + uint32_t picsr; /* Interrupt contrl register*/ #endif uint32_t fpcsr; /* Float register */ float_status fp_status; @@ -274,6 +277,8 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenriscState *env, target_ulong address, void openrisc_reset(CPUOpenriscState *env); #if !defined(CONFIG_USER_ONLY) void cpu_openrisc_pic_reset(CPUOpenriscState *env); +void cpu_openrisc_store_picsr(CPUOpenriscState *env, uint32_t value); +void cpu_openrisc_store_picmr(CPUOpenriscState *env, uint32_t value); void openrisc_mmu_init(CPUOpenriscState *env); int get_phys_nommu(CPUOpenriscState *env, target_phys_addr_t *physical, -- 1.7.9.5