From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SYeZ1-0002bg-UA for qemu-devel@nongnu.org; Sun, 27 May 2012 10:35:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SYeZ0-00071Y-3l for qemu-devel@nongnu.org; Sun, 27 May 2012 10:35:23 -0400 Received: from mail-lpp01m010-f45.google.com ([209.85.215.45]:33332) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SYeYz-00071N-Pt for qemu-devel@nongnu.org; Sun, 27 May 2012 10:35:22 -0400 Received: by lahc1 with SMTP id c1so1822731lah.4 for ; Sun, 27 May 2012 07:35:19 -0700 (PDT) From: Max Filippov Date: Sun, 27 May 2012 18:34:53 +0400 Message-Id: <1338129294-16742-6-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1338129294-16742-1-git-send-email-jcmvbkbc@gmail.com> References: <1338129294-16742-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 1.1 5/6] target-xtensa: control page table lookup explicitly List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Max Filippov , Anthony Liguori Hardware pagetable walking may not be nested. Stop guessing and pass explicit flag to the get_physical_addr_mmu function that controls page table lookup. Signed-off-by: Max Filippov --- target-xtensa/helper.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 86c33d2..8ebef72 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -452,7 +452,8 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, unsigned *access) + uint32_t *paddr, uint32_t *page_size, unsigned *access, + bool may_lookup_pt) { bool dtlb = is_write != 2; uint32_t wi; @@ -465,8 +466,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && - (mmu_idx != 0 || ((vaddr ^ env->sregs[PTEVADDR]) & 0xffc00000)) && - get_pte(env, vaddr, &pte) == 0) { + may_lookup_pt && get_pte(env, vaddr, &pte) == 0) { ring = (pte >> 4) & 0x3; wi = 0; split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); @@ -520,7 +520,7 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) uint32_t pt_vaddr = (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, - &paddr, &page_size, &access); + &paddr, &page_size, &access, false); qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__, vaddr, ret ? ~0 : paddr); @@ -568,7 +568,7 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { return get_physical_addr_mmu(env, update_tlb, - vaddr, is_write, mmu_idx, paddr, page_size, access); + vaddr, is_write, mmu_idx, paddr, page_size, access, true); } else if (xtensa_option_bits_enabled(env->config, XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { -- 1.7.7.6