From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ScFLt-0006GN-2E for qemu-devel@nongnu.org; Wed, 06 Jun 2012 08:28:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ScFLq-0006dy-Rm for qemu-devel@nongnu.org; Wed, 06 Jun 2012 08:28:40 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:38710) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ScFLq-0006I0-IX for qemu-devel@nongnu.org; Wed, 06 Jun 2012 08:28:38 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so9665647pbb.4 for ; Wed, 06 Jun 2012 05:28:37 -0700 (PDT) From: Jia Liu Date: Wed, 6 Jun 2012 20:27:06 +0800 Message-Id: <1338985632-29597-11-git-send-email-proljc@gmail.com> In-Reply-To: <1338985632-29597-1-git-send-email-proljc@gmail.com> References: <1338985632-29597-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH v3 10/16] target-or32: Add timer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Add a OpenRISC timer. Signed-off-by: Jia Liu --- hw/openrisc_timer.c | 130 +++++++++++++++++++++++++++++++++++++++++++++++++ target-openrisc/cpu.h | 3 ++ 2 files changed, 133 insertions(+) diff --git a/hw/openrisc_timer.c b/hw/openrisc_timer.c index df384f6..1d657a6 100644 --- a/hw/openrisc_timer.c +++ b/hw/openrisc_timer.c @@ -22,9 +22,139 @@ #include "openrisc_cpudev.h" #include "qemu-timer.h" +#define TIMER_FREQ (20 * 1000 * 1000) /* 20MHz */ + +/* The time when ttcr changes */ +static uint64_t last_clk; +static int is_counting; + +/* Timer Mode */ +enum { + TIMER_NONE = (0<<30), + TIMER_INTR = (1<<30), + TIMER_SHOT = (2<<30), + TIMER_CONT = (3<<30), +}; + /* Reset Timer */ void cpu_openrisc_timer_reset(CPUOpenRISCState *env) { env->ttmr = 0x00000000; env->ttcr = 0x00000000; } + +static void count_update(CPUOpenRISCState *env) +{ + uint64_t now, next; + uint32_t wait; + + now = qemu_get_clock_ns(vm_clock); + if (!is_counting) { + qemu_del_timer(env->timer); + last_clk = now; + return; + } + + env->ttcr += (uint32_t)muldiv64(now - last_clk, TIMER_FREQ, + get_ticks_per_sec()); + last_clk = now; + + if ((env->ttmr & TTMR_TP) <= (env->ttcr & TTMR_TP)) { + wait = TTMR_TP - (env->ttcr & TTMR_TP) + 1; + wait += env->ttmr & TTMR_TP; + } else { + wait = (env->ttmr & TTMR_TP) - (env->ttcr & TTMR_TP); + } + + next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ); + qemu_mod_timer(env->timer, next); +} + +static void count_start(CPUOpenRISCState *env) +{ + is_counting = 1; + count_update(env); +} + +static void count_stop(CPUOpenRISCState *env) +{ + is_counting = 0; + count_update(env); +} + +uint32_t cpu_openrisc_get_count(CPUOpenRISCState *env) +{ + count_update(env); + return env->ttcr; +} + +void cpu_openrisc_store_count(CPUOpenRISCState *env, uint32_t count) +{ + /* Store new count register */ + env->ttcr = count; + if (env->ttmr & TIMER_NONE) { + return; + } + count_start(env); +} + +void cpu_openrisc_store_compare(CPUOpenRISCState *env, uint32_t value) +{ + int ip = env->ttmr & TTMR_IP; + + if (value & TTMR_IP) { /* Keep IP bit */ + env->ttmr = (value & ~TTMR_IP) + ip; + } else { /* Clear IP bit */ + env->ttmr = value & ~TTMR_IP; + env->interrupt_request &= ~CPU_INTERRUPT_TIMER; + } + count_update(env); + + switch (env->ttmr & TTMR_M) { + case TIMER_NONE: + count_stop(env); + break; + case TIMER_INTR: + count_start(env); + break; + case TIMER_SHOT: + count_start(env); + break; + case TIMER_CONT: + count_start(env); + break; + } +} + +static void openrisc_timer_cb(void *opaque) +{ + CPUOpenRISCState *env = opaque; + + if ((env->ttmr & TTMR_IE) && + qemu_timer_expired(env->timer, qemu_get_clock_ns(vm_clock))) { + env->ttmr |= TTMR_IP; + env->interrupt_request |= CPU_INTERRUPT_TIMER; + } + + switch (env->ttmr & TTMR_M) { + case TIMER_NONE: + break; + case TIMER_INTR: + env->ttcr = 0; + count_start(env); + break; + case TIMER_SHOT: + count_stop(env); + break; + case TIMER_CONT: + count_start(env); + break; + } +} + +void cpu_openrisc_clock_init(CPUOpenRISCState *env) +{ + env->timer = qemu_new_timer_ns(vm_clock, &openrisc_timer_cb, env); + env->ttmr = 0; + env->ttcr = 0; +} diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 27f705b..202d9fa 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -332,6 +332,9 @@ void cpu_openrisc_store_picsr(CPUOpenRISCState *env, uint32_t value); void cpu_openrisc_store_picmr(CPUOpenRISCState *env, uint32_t value); void cpu_openrisc_timer_reset(CPUOpenRISCState *env); +void cpu_openrisc_store_count(CPUOpenRISCState *env, target_ulong count); +void cpu_openrisc_store_compare(CPUOpenRISCState *env, target_ulong value); +uint32_t cpu_openrisc_get_count(CPUOpenRISCState *env); void openrisc_mmu_init(CPUOpenRISCState *env); int get_phys_nommu(CPUOpenRISCState *env, target_phys_addr_t *physical, -- 1.7.9.5