From: Jia Liu <proljc@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v3 07/16] target-or32: Add float instruction helpers
Date: Wed, 6 Jun 2012 20:27:03 +0800 [thread overview]
Message-ID: <1338985632-29597-8-git-send-email-proljc@gmail.com> (raw)
In-Reply-To: <1338985632-29597-1-git-send-email-proljc@gmail.com>
Add OpenRISC float instruction helpers.
Signed-off-by: Jia Liu <proljc@gmail.com>
---
Makefile.target | 4 +-
target-openrisc/fpu_helper.c | 275 ++++++++++++++++++++++++++++++++++++++++++
target-openrisc/helper.h | 33 +++++
3 files changed, 310 insertions(+), 2 deletions(-)
create mode 100644 target-openrisc/fpu_helper.c
diff --git a/Makefile.target b/Makefile.target
index 4f40fa5..89b0a4b 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -103,8 +103,8 @@ endif
libobj-$(TARGET_SPARC) += int32_helper.o
libobj-$(TARGET_SPARC64) += int64_helper.o
libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o mem_helper.o
-libobj-$(TARGET_OPENRISC) += excp.o excp_helper.o int_helper.o intrpt.o \
- intrpt_helper.o mmu.o mmu_helper.o
+libobj-$(TARGET_OPENRISC) += excp.o excp_helper.o fpu_helper.o int_helper.o \
+ intrpt.o intrpt_helper.o mmu.o mmu_helper.o
libobj-y += disas.o
libobj-$(CONFIG_TCI_DIS) += tci-dis.o
diff --git a/target-openrisc/fpu_helper.c b/target-openrisc/fpu_helper.c
new file mode 100644
index 0000000..40f5857
--- /dev/null
+++ b/target-openrisc/fpu_helper.c
@@ -0,0 +1,275 @@
+/*
+ * OpenRISC float helper routines
+ *
+ * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ * Feng Gao <gf91597@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "helper.h"
+#include "excp.h"
+
+static inline uint32_t ieee_ex_to_openrisc(CPUOpenRISCState *env, int fexcp)
+{
+ int ret = 0;
+ if (fexcp) {
+ if (fexcp & float_flag_invalid) {
+ env->fpcsr |= FPCSR_IVF;
+ ret = 1;
+ }
+ if (fexcp & float_flag_overflow) {
+ env->fpcsr |= FPCSR_OVF;
+ ret = 1;
+ }
+ if (fexcp & float_flag_underflow) {
+ env->fpcsr |= FPCSR_UNF;
+ ret = 1;
+ }
+ if (fexcp & float_flag_divbyzero) {
+ env->fpcsr |= FPCSR_DZF;
+ ret = 1;
+ }
+ if (fexcp & float_flag_inexact) {
+ env->fpcsr |= FPCSR_IXF;
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static inline void update_fpcsr(CPUOpenRISCState *env)
+{
+ int tmp = ieee_ex_to_openrisc(env,
+ get_float_exception_flags(&env->fp_status));
+
+ SET_FP_CAUSE(env->fpcsr, tmp);
+ if ((GET_FP_ENABLE(env->fpcsr) & tmp) && (env->fpcsr & FPCSR_FPEE)) {
+ helper_exception(env, EXCP_FPE);
+ } else {
+ UPDATE_FP_FLAGS(env->fpcsr, tmp);
+ }
+}
+
+uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
+{
+ uint64_t itofd;
+ set_float_exception_flags(0, &env->fp_status);
+ itofd = int32_to_float64(val, &env->fp_status);
+ update_fpcsr(env);
+ return itofd;
+}
+
+uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val)
+{
+ uint32_t itofs;
+ set_float_exception_flags(0, &env->fp_status);
+ itofs = int32_to_float32(val, &env->fp_status);
+ update_fpcsr(env);
+ return itofs;
+}
+
+uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
+{
+ uint64_t ftoid;
+ set_float_exception_flags(0, &env->fp_status);
+ ftoid = float32_to_int64(val, &env->fp_status);
+ update_fpcsr(env);
+ return ftoid;
+}
+
+uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
+{
+ uint32_t ftois;
+ set_float_exception_flags(0, &env->fp_status);
+ ftois = float32_to_int32(val, &env->fp_status);
+ update_fpcsr(env);
+ return ftois;
+}
+
+#define FLOAT_OP(name, p) void helper_float_##_##p(void)
+
+#define FLOAT_CALC(name) \
+uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, uint64_t fdt1) \
+{ \
+ uint64_t result; \
+ set_float_exception_flags(0, &env->fp_status); \
+ result = float64_ ## name(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return result; \
+} \
+ \
+uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1) \
+{ \
+ uint32_t result; \
+ set_float_exception_flags(0, &env->fp_status); \
+ result = float32_ ## name(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return result; \
+} \
+
+FLOAT_CALC(add)
+FLOAT_CALC(sub)
+FLOAT_CALC(mul)
+FLOAT_CALC(div)
+FLOAT_CALC(rem)
+#undef FLOAT_CALC
+
+#define FLOAT_TERNOP(name1, name2) \
+uint64_t helper_float_ ## name1 ## name2 ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, \
+ uint64_t fdt1) \
+{ \
+ uint64_t result, temp, hi, lo; \
+ uint32_t val1, val2; \
+ hi = env->fpmaddhi; \
+ lo = env->fpmaddlo; \
+ set_float_exception_flags(0, &env->fp_status); \
+ result = float64_ ## name1(fdt0, fdt1, &env->fp_status); \
+ lo &= 0xffffffff; \
+ hi &= 0xffffffff; \
+ temp = (hi << 32) | lo; \
+ result = float64_ ## name2(result, temp, &env->fp_status); \
+ val1 = result >> 32; \
+ val2 = (uint32_t) (result & 0xffffffff); \
+ update_fpcsr(env); \
+ env->fpmaddlo = val2; \
+ env->fpmaddhi = val1; \
+ return 0; \
+} \
+ \
+uint32_t helper_float_ ## name1 ## name2 ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1) \
+{ \
+ uint64_t result, temp, hi, lo; \
+ uint32_t val1, val2; \
+ hi = env->fpmaddhi; \
+ lo = env->fpmaddlo; \
+ set_float_exception_flags(0, &env->fp_status); \
+ result = float64_ ## name1(fdt0, fdt1, &env->fp_status); \
+ temp = (hi << 32) | lo; \
+ result = float64_ ## name2(result, temp, &env->fp_status); \
+ val1 = result >> 32; \
+ val2 = (uint32_t) (result & 0xffffffff); \
+ update_fpcsr(env); \
+ env->fpmaddlo = val2; \
+ env->fpmaddhi = val1; \
+ return 0; \
+}
+
+FLOAT_TERNOP(mul, add)
+#undef FLOAT_TERNOP
+
+
+#define FLOAT_CMP(name) \
+uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, uint64_t fdt1) \
+{ \
+ int res; \
+ set_float_exception_flags(0, &env->fp_status); \
+ res = float64_ ## name(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return res; \
+} \
+ \
+uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1)\
+{ \
+ int res; \
+ set_float_exception_flags(0, &env->fp_status); \
+ res = float32_ ## name(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return res; \
+}
+
+FLOAT_CMP(le)
+FLOAT_CMP(eq)
+FLOAT_CMP(lt)
+#undef FLOAT_CMP
+
+
+#define FLOAT_CMPNE(name) \
+uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, uint64_t fdt1) \
+{ \
+ int res; \
+ set_float_exception_flags(0, &env->fp_status); \
+ res = !float64_eq_quiet(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return res; \
+} \
+ \
+uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1) \
+{ \
+ int res; \
+ set_float_exception_flags(0, &env->fp_status); \
+ res = !float32_eq_quiet(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return res; \
+}
+
+FLOAT_CMPNE(ne)
+#undef FLOAT_CMPNE
+
+#define FLOAT_CMPGT(name) \
+uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, uint64_t fdt1) \
+{ \
+ int res; \
+ set_float_exception_flags(0, &env->fp_status); \
+ res = !float64_le(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return res; \
+} \
+ \
+uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1) \
+{ \
+ int res; \
+ set_float_exception_flags(0, &env->fp_status); \
+ res = !float32_le(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return res; \
+}
+FLOAT_CMPGT(gt)
+#undef FLOAT_CMPGT
+
+#define FLOAT_CMPGE(name) \
+uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, uint64_t fdt1) \
+{ \
+ int res; \
+ set_float_exception_flags(0, &env->fp_status); \
+ res = !float64_lt(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return res; \
+} \
+ \
+uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1) \
+{ \
+ int res; \
+ set_float_exception_flags(0, &env->fp_status); \
+ res = !float32_lt(fdt0, fdt1, &env->fp_status); \
+ update_fpcsr(env); \
+ return res; \
+}
+
+FLOAT_CMPGE(ge)
+#undef FLOAT_CMPGE
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
index df354a5..b3c1a17 100644
--- a/target-openrisc/helper.h
+++ b/target-openrisc/helper.h
@@ -22,6 +22,39 @@
/* exception */
DEF_HELPER_FLAGS_2(exception, 0, void, env, i32)
+/* float */
+DEF_HELPER_FLAGS_2(itofd, 0, i64, env, i64)
+DEF_HELPER_FLAGS_2(itofs, 0, i32, env, i32)
+DEF_HELPER_FLAGS_2(ftoid, 0, i64, env, i64)
+DEF_HELPER_FLAGS_2(ftois, 0, i32, env, i32)
+
+#define FOP_MADD(op) \
+DEF_HELPER_FLAGS_3(float_ ## op ## _s, 0, i32, env, i32, i32) \
+DEF_HELPER_FLAGS_3(float_ ## op ## _d, 0, i64, env, i64, i64)
+FOP_MADD(muladd)
+#undef FOP_MADD
+
+#define FOP_CALC(op) \
+DEF_HELPER_FLAGS_3(float_ ## op ## _s, 0, i32, env, i32, i32) \
+DEF_HELPER_FLAGS_3(float_ ## op ## _d, 0, i64, env, i64, i64)
+FOP_CALC(add)
+FOP_CALC(sub)
+FOP_CALC(mul)
+FOP_CALC(div)
+FOP_CALC(rem)
+#undef FOP_CALC
+
+#define FOP_CMP(op) \
+DEF_HELPER_FLAGS_3(float_ ## op ## _s, 0, i32, env, i32, i32) \
+DEF_HELPER_FLAGS_3(float_ ## op ## _d, 0, i64, env, i64, i64)
+FOP_CMP(eq)
+FOP_CMP(lt)
+FOP_CMP(le)
+FOP_CMP(ne)
+FOP_CMP(gt)
+FOP_CMP(ge)
+#undef FOP_CMP
+
/* int */
DEF_HELPER_FLAGS_1(ff1, 0, tl, tl)
DEF_HELPER_FLAGS_1(fl1, 0, tl, tl)
--
1.7.9.5
next prev parent reply other threads:[~2012-06-06 12:28 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-06 12:26 [Qemu-devel] [PATCH v3 00/16] target-or32: QEMU OpenRISC support Jia Liu
2012-06-06 12:26 ` [Qemu-devel] [PATCH v3 01/16] target-or32: Add target stubs and cpu QOM Jia Liu
2012-06-06 12:26 ` [Qemu-devel] [PATCH v3 02/16] target-or32: Add target machine Jia Liu
2012-06-06 12:26 ` [Qemu-devel] [PATCH v3 03/16] target-or32: Add MMU support Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 04/16] target-or32: Add interrupt support Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 05/16] target-or32: Add exception support Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 06/16] target-or32: Add int instruction helpers Jia Liu
2012-06-06 12:27 ` Jia Liu [this message]
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 08/16] target-or32: Add translation routines Jia Liu
2012-06-06 16:40 ` Max Filippov
2012-06-08 0:00 ` Jia Liu
2012-06-08 0:21 ` Richard Henderson
2012-06-08 2:16 ` Jia Liu
2012-06-08 2:58 ` 陳韋任 (Wei-Ren Chen)
2012-06-08 12:56 ` Max Filippov
2012-06-08 13:28 ` Andreas Färber
2012-06-08 13:31 ` Andreas Färber
2012-06-08 22:12 ` Jia Liu
2012-06-08 21:59 ` Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 09/16] target-or32: Add PIC support Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 10/16] target-or32: Add timer Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 11/16] target-or32: Add a IIS dummy board Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 12/16] target-or32: Add system instruction helpers Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 13/16] target-or32: Add gdb stub Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 14/16] target-or32: Add linux syscall, signal and termbits Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 15/16] target-or32: Add linux user support Jia Liu
2012-06-06 12:27 ` [Qemu-devel] [PATCH v3 16/16] target-or32: Add testcases Jia Liu
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