From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34385) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sds4T-00027r-5R for qemu-devel@nongnu.org; Sun, 10 Jun 2012 20:01:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sds4R-0006Mr-6J for qemu-devel@nongnu.org; Sun, 10 Jun 2012 20:01:24 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43955 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sds4Q-0006Mf-SP for qemu-devel@nongnu.org; Sun, 10 Jun 2012 20:01:23 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 11 Jun 2012 02:00:44 +0200 Message-Id: <1339372859-30148-13-git-send-email-afaerber@suse.de> In-Reply-To: <1339372859-30148-1-git-send-email-afaerber@suse.de> References: <1339372859-30148-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 12/27] arm_boot: Pass ARMCPU to arm_boot_info::write_secondary_boot() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , Evgeny Voevodin , Mark Langsdorf , Dmitry Solodkiy , Maksim Kozlov , =?UTF-8?q?Andreas=20F=C3=A4rber?= Adapt exynos4210 and highbank accordingly. The parameter itself is unused. Signed-off-by: Andreas F=C3=A4rber Acked-by: Peter Maydell Acked-by: Igor Mitsyanko (for exynos) --- hw/arm-misc.h | 2 +- hw/arm_boot.c | 6 +++--- hw/exynos4210.c | 2 +- hw/exynos4210.h | 2 +- hw/highbank.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 2f46e21..320033d 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -50,7 +50,7 @@ struct arm_boot_info { * perform any necessary CPU reset handling and set the PC for thei * secondary CPUs to point at this boot blob. */ - void (*write_secondary_boot)(CPUARMState *env, + void (*write_secondary_boot)(ARMCPU *cpu, const struct arm_boot_info *info); void (*secondary_cpu_reset_hook)(CPUARMState *env, const struct arm_boot_info *info); diff --git a/hw/arm_boot.c b/hw/arm_boot.c index eb2d176..4955f01 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -59,7 +59,7 @@ static uint32_t smpboot[] =3D { 0 /* bootreg: Boot register address is held here */ }; =20 -static void default_write_secondary(CPUARMState *env, +static void default_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { int n; @@ -303,7 +303,7 @@ static void do_cpu_reset(void *opaque) =20 void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info) { - ARMCPU *cpu; + ARMCPU *cpu =3D arm_env_get_cpu(env); int kernel_size; int initrd_size; int n; @@ -402,7 +402,7 @@ void arm_load_kernel(CPUARMState *env, struct arm_boo= t_info *info) rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader), info->loader_start); if (info->nb_cpus > 1) { - info->write_secondary_boot(env, info); + info->write_secondary_boot(cpu, info); } } info->is_linux =3D is_linux; diff --git a/hw/exynos4210.c b/hw/exynos4210.c index afc4bdc..ae53837 100644 --- a/hw/exynos4210.c +++ b/hw/exynos4210.c @@ -65,7 +65,7 @@ static uint8_t chipid_and_omr[] =3D { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; =20 -void exynos4210_write_secondary(CPUARMState *env, +void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { int n; diff --git a/hw/exynos4210.h b/hw/exynos4210.h index f7c7027..b520676 100644 --- a/hw/exynos4210.h +++ b/hw/exynos4210.h @@ -97,7 +97,7 @@ typedef struct Exynos4210State { MemoryRegion bootreg_mem; } Exynos4210State; =20 -void exynos4210_write_secondary(CPUARMState *env, +void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info); =20 Exynos4210State *exynos4210_init(MemoryRegion *system_mem, diff --git a/hw/highbank.c b/hw/highbank.c index 4d6d728..45ca1ad 100644 --- a/hw/highbank.c +++ b/hw/highbank.c @@ -36,7 +36,7 @@ =20 /* Board init. */ =20 -static void hb_write_secondary(CPUARMState *env, const struct arm_boot_i= nfo *info) +static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *= info) { int n; uint32_t smpboot[] =3D { --=20 1.7.7