From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34446) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sds4Y-0002NC-3O for qemu-devel@nongnu.org; Sun, 10 Jun 2012 20:01:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sds4W-0006Oc-92 for qemu-devel@nongnu.org; Sun, 10 Jun 2012 20:01:29 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43970 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sds4V-0006OF-Vq for qemu-devel@nongnu.org; Sun, 10 Jun 2012 20:01:28 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id C4B5890B49 for ; Mon, 11 Jun 2012 02:01:26 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 11 Jun 2012 02:00:50 +0200 Message-Id: <1339372859-30148-19-git-send-email-afaerber@suse.de> In-Reply-To: <1339372859-30148-1-git-send-email-afaerber@suse.de> References: <1339372859-30148-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 18/27] pxa2xx_pic: Store ARMCPU in PXA2xxPICState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Prepares for moving halted field to CPUState. Add missing braces. Signed-off-by: Andreas F=C3=A4rber Acked-by: Peter Maydell --- hw/pxa2xx_pic.c | 29 ++++++++++++++++------------- 1 files changed, 16 insertions(+), 13 deletions(-) diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c index 255cc3f..c560133 100644 --- a/hw/pxa2xx_pic.c +++ b/hw/pxa2xx_pic.c @@ -34,7 +34,7 @@ typedef struct { SysBusDevice busdev; MemoryRegion iomem; - CPUARMState *cpu_env; + ARMCPU *cpu; uint32_t int_enabled[2]; uint32_t int_pending[2]; uint32_t is_fiq[2]; @@ -47,25 +47,28 @@ static void pxa2xx_pic_update(void *opaque) uint32_t mask[2]; PXA2xxPICState *s =3D (PXA2xxPICState *) opaque; =20 - if (s->cpu_env->halted) { + if (s->cpu->env.halted) { mask[0] =3D s->int_pending[0] & (s->int_enabled[0] | s->int_idle= ); mask[1] =3D s->int_pending[1] & (s->int_enabled[1] | s->int_idle= ); - if (mask[0] || mask[1]) - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB); + if (mask[0] || mask[1]) { + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB); + } } =20 mask[0] =3D s->int_pending[0] & s->int_enabled[0]; mask[1] =3D s->int_pending[1] & s->int_enabled[1]; =20 - if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ); - else - cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ); + if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) { + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ); + } else { + cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ); + } =20 - if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); - else - cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) { + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); + } } =20 /* Note: Here level means state of the signal on a pin, not @@ -251,7 +254,7 @@ DeviceState *pxa2xx_pic_init(target_phys_addr_t base,= ARMCPU *cpu) DeviceState *dev =3D qdev_create(NULL, "pxa2xx_pic"); PXA2xxPICState *s =3D FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(d= ev)); =20 - s->cpu_env =3D env; + s->cpu =3D cpu; =20 s->int_pending[0] =3D 0; s->int_pending[1] =3D 0; --=20 1.7.7