From: Jia Liu <proljc@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v4 13/16] target-or32: Add gdb stub support
Date: Mon, 11 Jun 2012 14:32:01 +0800 [thread overview]
Message-ID: <1339396324-21368-14-git-send-email-proljc@gmail.com> (raw)
In-Reply-To: <1339396324-21368-1-git-send-email-proljc@gmail.com>
Add OpenRISC gdb stub support.
Signed-off-by: Jia Liu <proljc@gmail.com>
---
gdbstub.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index 08cf864..5d37dd9 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1155,6 +1155,68 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
return sizeof(target_ulong);
}
+#elif defined(TARGET_OPENRISC)
+
+#define NUM_CORE_REGS (32 + 3)
+
+static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ GET_REG32(env->gpr[n]);
+ } else {
+ switch (n) {
+ case 32: /* PPC */
+ GET_REG32(env->ppc);
+ break;
+
+ case 33: /* NPC */
+ GET_REG32(env->npc);
+ break;
+
+ case 34: /* SR */
+ GET_REG32(env->sr);
+ break;
+
+ default:
+ break;
+ }
+ }
+ return 0;
+}
+
+static int cpu_gdb_write_register(CPUOpenRISCState *env,
+ uint8_t *mem_buf, int n)
+{
+ uint32_t tmp;
+
+ if (n > NUM_CORE_REGS) {
+ return 0;
+ }
+
+ tmp = ldl_p(mem_buf);
+
+ if (n < 32) {
+ env->gpr[n] = tmp;
+ } else {
+ switch (n) {
+ case 32: /* PPC */
+ env->ppc = tmp;
+ break;
+
+ case 33: /* NPC */
+ env->npc = tmp;
+ break;
+
+ case 34: /* SR */
+ env->sr = tmp;
+ break;
+
+ default:
+ break;
+ }
+ }
+ return 4;
+}
#elif defined (TARGET_SH4)
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
@@ -1924,6 +1986,8 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
}
#elif defined (TARGET_MICROBLAZE)
s->c_cpu->sregs[SR_PC] = pc;
+#elif defined(TARGET_OPENRISC)
+ s->c_cpu->pc = pc;
#elif defined (TARGET_CRIS)
s->c_cpu->pc = pc;
#elif defined (TARGET_ALPHA)
--
1.7.9.5
next prev parent reply other threads:[~2012-06-11 6:34 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-11 6:31 [Qemu-devel] [PATCH v4 00/16] QEMU OpenRISC support Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 01/16] target-or32: Add target stubs and cpu support Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 02/16] target-or32: Add target machine Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 03/16] target-or32: Add MMU support Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 04/16] target-or32: Add interrupt support Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 05/16] target-or32: Add exception support Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 06/16] target-or32: Add int instruction helpers Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 07/16] target-or32: Add float " Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 08/16] target-or32: Add translation routines Jia Liu
2012-06-13 18:59 ` Blue Swirl
2012-06-17 23:56 ` Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 09/16] target-or32: Add PIC support Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 10/16] target-or32: Add timer support Jia Liu
2012-06-11 6:31 ` [Qemu-devel] [PATCH v4 11/16] target-or32: Add a IIS dummy board Jia Liu
2012-06-11 6:32 ` [Qemu-devel] [PATCH v4 12/16] target-or32: Add system instructions Jia Liu
2012-06-13 18:35 ` Blue Swirl
2012-06-17 8:40 ` Jia Liu
2012-06-11 6:32 ` Jia Liu [this message]
2012-06-11 6:32 ` [Qemu-devel] [PATCH v4 14/16] target-or32: Add linux syscall, signal and termbits Jia Liu
2012-06-11 6:32 ` [Qemu-devel] [PATCH v4 15/16] target-or32: Add linux user support Jia Liu
2012-06-11 6:32 ` [Qemu-devel] [PATCH v4 16/16] target-or32: Add testcases Jia Liu
2012-06-17 21:37 ` [Qemu-devel] [PATCH v4 00/16] QEMU OpenRISC support Max Filippov
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