From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:44944) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfWfM-0001cG-Vv for qemu-devel@nongnu.org; Fri, 15 Jun 2012 09:34:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SfWfK-0004pP-PQ for qemu-devel@nongnu.org; Fri, 15 Jun 2012 09:34:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36258) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SfWfK-0004or-Hy for qemu-devel@nongnu.org; Fri, 15 Jun 2012 09:34:18 -0400 From: Kevin Wolf Date: Fri, 15 Jun 2012 15:33:25 +0200 Message-Id: <1339767219-24297-26-git-send-email-kwolf@redhat.com> In-Reply-To: <1339767219-24297-1-git-send-email-kwolf@redhat.com> References: <1339767219-24297-1-git-send-email-kwolf@redhat.com> Subject: [Qemu-devel] [PATCH 25/39] ide: support enable/disable write cache List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: anthony@codemonkey.ws Cc: kwolf@redhat.com, qemu-devel@nongnu.org From: Paolo Bonzini Enabling or disabling the write cache is done with the SET FEATURES command. The command can be issued with sg_sat_set_features from sg3-utils. Signed-off-by: Paolo Bonzini Signed-off-by: Kevin Wolf --- hw/ide/core.c | 21 ++++++++++++++++++--- 1 files changed, 18 insertions(+), 3 deletions(-) diff --git a/hw/ide/core.c b/hw/ide/core.c index 9785d5f..f28229a 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -1047,6 +1047,7 @@ static bool ide_cmd_permitted(IDEState *s, uint32_t cmd) void ide_exec_cmd(IDEBus *bus, uint32_t val) { + uint16_t *identify_data; IDEState *s; int n; int lba48 = 0; @@ -1231,10 +1232,21 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val) goto abort_cmd; /* XXX: valid for CDROM ? */ switch(s->feature) { - case 0xcc: /* reverting to power-on defaults enable */ - case 0x66: /* reverting to power-on defaults disable */ case 0x02: /* write cache enable */ + bdrv_set_enable_write_cache(s->bs, true); + identify_data = (uint16_t *)s->identify_data; + put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1); + s->status = READY_STAT | SEEK_STAT; + ide_set_irq(s->bus); + break; case 0x82: /* write cache disable */ + bdrv_set_enable_write_cache(s->bs, false); + identify_data = (uint16_t *)s->identify_data; + put_le16(identify_data + 85, (1 << 14) | 1); + ide_flush_cache(s); + break; + case 0xcc: /* reverting to power-on defaults enable */ + case 0x66: /* reverting to power-on defaults disable */ case 0xaa: /* read look-ahead enable */ case 0x55: /* read look-ahead disable */ case 0x05: /* set advanced power management mode */ @@ -1250,7 +1262,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val) break; case 0x03: { /* set transfer mode */ uint8_t val = s->nsector & 0x07; - uint16_t *identify_data = (uint16_t *)s->identify_data; + identify_data = (uint16_t *)s->identify_data; switch (s->nsector >> 3) { case 0x00: /* pio default */ @@ -2146,6 +2158,9 @@ static int ide_drive_post_load(void *opaque, int version_id) s->cdrom_changed = 1; } } + if (s->identify_set) { + bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5))); + } return 0; } -- 1.7.6.5