From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOk-0002ud-EC for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SgQOi-00059J-NT for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:53 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:43016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOi-0004jq-Ez for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:52 -0400 Received: by mail-pz0-f45.google.com with SMTP id n2so5607657dad.4 for ; Sun, 17 Jun 2012 18:04:51 -0700 (PDT) From: Jia Liu Date: Mon, 18 Jun 2012 09:03:01 +0800 Message-Id: <1339981384-9117-14-git-send-email-proljc@gmail.com> In-Reply-To: <1339981384-9117-1-git-send-email-proljc@gmail.com> References: <1339981384-9117-1-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset="utf-8" Subject: [Qemu-devel] [PATCH v5 13/16] target-or32: Add gdb stub support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Add QEMU OpenRISC gdb stub support. Signed-off-by: Jia Liu --- gdbstub.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 08cf864..5d37dd9 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1155,6 +1155,68 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n) return sizeof(target_ulong); } +#elif defined(TARGET_OPENRISC) + +#define NUM_CORE_REGS (32 + 3) + +static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + GET_REG32(env->gpr[n]); + } else { + switch (n) { + case 32: /* PPC */ + GET_REG32(env->ppc); + break; + + case 33: /* NPC */ + GET_REG32(env->npc); + break; + + case 34: /* SR */ + GET_REG32(env->sr); + break; + + default: + break; + } + } + return 0; +} + +static int cpu_gdb_write_register(CPUOpenRISCState *env, + uint8_t *mem_buf, int n) +{ + uint32_t tmp; + + if (n > NUM_CORE_REGS) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->gpr[n] = tmp; + } else { + switch (n) { + case 32: /* PPC */ + env->ppc = tmp; + break; + + case 33: /* NPC */ + env->npc = tmp; + break; + + case 34: /* SR */ + env->sr = tmp; + break; + + default: + break; + } + } + return 4; +} #elif defined (TARGET_SH4) /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ @@ -1924,6 +1986,8 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) } #elif defined (TARGET_MICROBLAZE) s->c_cpu->sregs[SR_PC] = pc; +#elif defined(TARGET_OPENRISC) + s->c_cpu->pc = pc; #elif defined (TARGET_CRIS) s->c_cpu->pc = pc; #elif defined (TARGET_ALPHA) -- 1.7.9.5