From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37937) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgcUw-0001fI-GF for qemu-devel@nongnu.org; Mon, 18 Jun 2012 10:00:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SgcUW-0003WX-6E for qemu-devel@nongnu.org; Mon, 18 Jun 2012 10:00:06 -0400 Received: from cantor2.suse.de ([195.135.220.15]:53243 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgcUV-0003Vy-Sb for qemu-devel@nongnu.org; Mon, 18 Jun 2012 09:59:40 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 18 Jun 2012 15:59:00 +0200 Message-Id: <1340027954-19045-9-git-send-email-afaerber@suse.de> In-Reply-To: <1340027954-19045-1-git-send-email-afaerber@suse.de> References: <1340027954-19045-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 08/22] m48t59: Rename "type" property to "model" List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Anthony Liguori From: Paolo Bonzini This resolves a name conflict with the qdev "type" property that is about to move into Object. Signed-off-by: Paolo Bonzini [AF: Add braces missing in original code.] Signed-off-by: Andreas F=C3=A4rber --- hw/m48t59.c | 40 ++++++++++++++++++++++------------------ 1 files changed, 22 insertions(+), 18 deletions(-) diff --git a/hw/m48t59.c b/hw/m48t59.c index 0c50f45..dd6cb37 100644 --- a/hw/m48t59.c +++ b/hw/m48t59.c @@ -65,7 +65,7 @@ struct M48t59State { /* NVRAM storage */ uint8_t *buffer; /* Model parameters */ - uint32_t type; /* 2 =3D m48t02, 8 =3D m48t08, 59 =3D m48t59 */ + uint32_t model; /* 2 =3D m48t02, 8 =3D m48t08, 59 =3D m48t59 */ /* NVRAM storage */ uint16_t addr; uint8_t lock; @@ -197,10 +197,11 @@ void m48t59_write (void *opaque, uint32_t addr, uin= t32_t val) NVRAM_PRINTF("%s: 0x%08x =3D> 0x%08x\n", __func__, addr, val); =20 /* check for NVRAM access */ - if ((NVRAM->type =3D=3D 2 && addr < 0x7f8) || - (NVRAM->type =3D=3D 8 && addr < 0x1ff8) || - (NVRAM->type =3D=3D 59 && addr < 0x1ff0)) + if ((NVRAM->model =3D=3D 2 && addr < 0x7f8) || + (NVRAM->model =3D=3D 8 && addr < 0x1ff8) || + (NVRAM->model =3D=3D 59 && addr < 0x1ff0)) { goto do_write; + } =20 /* TOD access */ switch (addr) { @@ -334,10 +335,11 @@ void m48t59_write (void *opaque, uint32_t addr, uin= t32_t val) tmp =3D from_bcd(val); if (tmp >=3D 0 && tmp <=3D 99) { get_time(NVRAM, &tm); - if (NVRAM->type =3D=3D 8) + if (NVRAM->model =3D=3D 8) { tm.tm_year =3D from_bcd(val) + 68; // Base year is 1968 - else + } else { tm.tm_year =3D from_bcd(val); + } set_time(NVRAM, &tm); } break; @@ -362,10 +364,11 @@ uint32_t m48t59_read (void *opaque, uint32_t addr) uint32_t retval =3D 0xFF; =20 /* check for NVRAM access */ - if ((NVRAM->type =3D=3D 2 && addr < 0x078f) || - (NVRAM->type =3D=3D 8 && addr < 0x1ff8) || - (NVRAM->type =3D=3D 59 && addr < 0x1ff0)) + if ((NVRAM->model =3D=3D 2 && addr < 0x078f) || + (NVRAM->model =3D=3D 8 && addr < 0x1ff8) || + (NVRAM->model =3D=3D 59 && addr < 0x1ff0)) { goto do_read; + } =20 /* TOD access */ switch (addr) { @@ -439,10 +442,11 @@ uint32_t m48t59_read (void *opaque, uint32_t addr) case 0x07FF: /* year */ get_time(NVRAM, &tm); - if (NVRAM->type =3D=3D 8) + if (NVRAM->model =3D=3D 8) { retval =3D to_bcd(tm.tm_year - 68); // Base year is 1968 - else + } else { retval =3D to_bcd(tm.tm_year); + } break; default: /* Check lock registers state */ @@ -633,7 +637,7 @@ static const MemoryRegionOps m48t59_io_ops =3D { =20 /* Initialisation routine */ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, - uint32_t io_base, uint16_t size, int type) + uint32_t io_base, uint16_t size, int model) { DeviceState *dev; SysBusDevice *s; @@ -641,7 +645,7 @@ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_ad= dr_t mem_base, M48t59State *state; =20 dev =3D qdev_create(NULL, "m48t59"); - qdev_prop_set_uint32(dev, "type", type); + qdev_prop_set_uint32(dev, "model", model); qdev_prop_set_uint32(dev, "size", size); qdev_prop_set_uint32(dev, "io_base", io_base); qdev_init_nofail(dev); @@ -661,14 +665,14 @@ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_= addr_t mem_base, } =20 M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t siz= e, - int type) + int model) { M48t59ISAState *d; ISADevice *dev; M48t59State *s; =20 dev =3D isa_create(bus, "m48t59_isa"); - qdev_prop_set_uint32(&dev->qdev, "type", type); + qdev_prop_set_uint32(&dev->qdev, "model", model); qdev_prop_set_uint32(&dev->qdev, "size", size); qdev_prop_set_uint32(&dev->qdev, "io_base", io_base); qdev_init_nofail(&dev->qdev); @@ -686,7 +690,7 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io= _base, uint16_t size, static void m48t59_init_common(M48t59State *s) { s->buffer =3D g_malloc0(s->size); - if (s->type =3D=3D 59) { + if (s->model =3D=3D 59) { s->alrm_timer =3D qemu_new_timer_ns(rtc_clock, &alarm_cb, s); s->wd_timer =3D qemu_new_timer_ns(vm_clock, &watchdog_cb, s); } @@ -722,7 +726,7 @@ static int m48t59_init1(SysBusDevice *dev) =20 static Property m48t59_isa_properties[] =3D { DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), - DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1), + DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -746,7 +750,7 @@ static TypeInfo m48t59_isa_info =3D { =20 static Property m48t59_properties[] =3D { DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), - DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1), + DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), DEFINE_PROP_END_OF_LIST(), }; --=20 1.7.7