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From: Peter Maydell <peter.maydell@linaro.org>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>,
	qemu-devel@nongnu.org, Paul Brook <paul@codesourcery.com>
Subject: [Qemu-devel] [PATCH 10/16] hw/arm_gic: Move CPU interface memory region setup into arm_gic_init
Date: Tue, 19 Jun 2012 14:31:07 +0100	[thread overview]
Message-ID: <1340112673-14846-11-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1340112673-14846-1-git-send-email-peter.maydell@linaro.org>

Remove more NVIC ifdefs by moving the code to setup the CPU interface
memory regions into the GIC specific arm_gic_init() function rather
than the gic_init() function. Rename the latter to more closely
reflect what it's now actually doing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm_gic.c     |   26 +++++++++++++-------------
 hw/armv7m_nvic.c |    2 +-
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index c288bc5..ad5ab3c 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -812,7 +812,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
-static void gic_init(gic_state *s, int num_irq)
+static void gic_init_irqs_and_distributor(gic_state *s, int num_irq)
 {
     int i;
 
@@ -850,7 +850,19 @@ static void gic_init(gic_state *s, int num_irq)
         sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
     }
     memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
+
+    register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
+}
+
 #ifndef NVIC
+
+static int arm_gic_init(SysBusDevice *dev)
+{
+    /* Device instance init function for the GIC sysbus device */
+    int i;
+    gic_state *s = FROM_SYSBUS(gic_state, dev);
+    gic_init_irqs_and_distributor(s, s->num_irq);
+
     /* Memory regions for the CPU interfaces (NVIC doesn't have these):
      * a region for "CPU interface for this core", then a region for
      * "CPU interface for core 0", "for core 1", ...
@@ -866,19 +878,7 @@ static void gic_init(gic_state *s, int num_irq)
         memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
                               "gic_cpu", 0x100);
     }
-#endif
-
-    register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
-}
-
-#ifndef NVIC
 
-static int arm_gic_init(SysBusDevice *dev)
-{
-    /* Device instance init function for the GIC sysbus device */
-    int i;
-    gic_state *s = FROM_SYSBUS(gic_state, dev);
-    gic_init(s, s->num_irq);
     /* Distributor */
     sysbus_init_mmio(dev, &s->iomem);
     /* cpu interfaces (one for "current cpu" plus one per cpu) */
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 4c130f1..031a7fd 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -449,7 +449,7 @@ static int armv7m_nvic_init(SysBusDevice *dev)
     s->gic.num_cpu = 1;
     /* Tell the common code we're an NVIC */
     s->gic.revision = 0xffffffff;
-    gic_init(&s->gic, s->num_irq);
+    gic_init_irqs_and_distributor(&s->gic, s->num_irq);
     /* The NVIC and system controller register area looks like this:
      *  0..0xff : system control registers, including systick
      *  0x100..0xcff : GIC-like registers
-- 
1.7.1

  parent reply	other threads:[~2012-06-19 13:56 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-19 13:30 [Qemu-devel] [PULL 00/16] arm-devs queue Peter Maydell
2012-06-19 13:30 ` [Qemu-devel] [PATCH 01/16] ARM: Exynos4210 IRQ: Introduce new IRQ gate functionality Peter Maydell
2012-06-19 13:30 ` [Qemu-devel] [PATCH 02/16] arm_boot: Fix typos in comment Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 03/16] hw/arm_gic: Remove NVIC ifdefs from gic_state struct Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 04/16] hw/arm_gic: Remove the special casing of NCPU for the NVIC Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 05/16] hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 06/16] hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 07/16] hw/arm_gic: Add qdev property for GIC revision Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 08/16] hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 09/16] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting Peter Maydell
2012-06-19 13:31 ` Peter Maydell [this message]
2012-06-19 13:31 ` [Qemu-devel] [PATCH 11/16] hw/armv7m_nvic: Make the NVIC a freestanding class Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 12/16] hw/omap.h: Drop broken MEM_VERBOSE tracing Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 13/16] hw/a9mpcore: Fix compilation failure if physaddrs are 64 bit Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 14/16] cadence_gem: avoid stack-writing buffer-overrun Peter Maydell
2012-06-20  1:47   ` Peter Crosthwaite
2012-06-19 13:31 ` [Qemu-devel] [PATCH 15/16] cadence_ttc: changed master clock frequency Peter Maydell
2012-06-19 13:31 ` [Qemu-devel] [PATCH 16/16] arm_boot: Conditionalised DTB command line update Peter Maydell
2012-06-24 12:26 ` [Qemu-devel] [PULL 00/16] arm-devs queue Blue Swirl

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